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NT5DS64M4AW PDF даташит

Спецификация NT5DS64M4AW изготовлена ​​​​«Nanya» и имеет функцию, называемую «(NT5DSxxMxAx) 256Mb DDR333/300 SDRAM».

Детали детали

Номер произв NT5DS64M4AW
Описание (NT5DSxxMxAx) 256Mb DDR333/300 SDRAM
Производители Nanya
логотип Nanya логотип 

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NT5DS64M4AW Даташит, Описание, Даташиты
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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Features
CAS Latency and Frequency
CAS Latency
Maximum Operating Frequency (MHz)*
DDR333 (-6)
DDR300 (-66)
2 133
133
2.5 166
150
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions.
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2, 2.5
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.5V ± 0.2V
• VDD = 2.5V ± 0.2V
• Package : 66pin TSOP-II / 60 balls 0.8mmx1.0mm pitch
CSP.
Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic
The DDR SDRAM provides for programmable Read or Write
random-access memory containing 268,435,456 bits. It is
burst lengths of 2, 4 or 8 locations. An Auto Precharge func-
internally configured as a quad-bank DRAM.
tion may be enabled to provide a self-timed row precharge
The 256Mb DDR SDRAM uses a double-data-rate architec-
that is initiated at the end of the burst access.
ture to achieve high-speed operation. The double data rate
As with standard SDRAMs, the pipelined, multibank architec-
architecture is essentially a 2n prefetch architecture with an
ture of DDR SDRAMs allows for concurrent operation,
interface designed to transfer two data words per clocDkactyacSleheet4thUe.rceobmy providing high effective bandwidth by hiding row pre-
at the I/O pins. A single read or write access for the 256Mb
charge and activation time.
DataShee
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
DataSheetP4Ure.cliomminary
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.









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NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Pin Configuration - 400mil TSOP II
et4U.com
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 57
11 56
12 55
13 54
14 53
15 52
16 51
17 50
18 49
19 48
20 47
21 46
22 45
D2a3taSheet4U.com 44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
66-pin Plastic TSOP-II 400mil
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
32Mb x 8
NT5DS32M8AT
64Mb x 4
NT5DS64M4AT
Column Address Table
Organization
64Mb x 4
Column Address
A0-A9, A11
32Mb x 8
A0-A9
*DM is internally loaded to match DQ and DQS identically.
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
DataShee
DataSheetP4Ure.cliomminary
10/01
DataSheet4 U .com
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.









No Preview Available !

NT5DS64M4AW Даташит, Описание, Даташиты
www.DataSheet4U.com
NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package
<Top View >
See the balls through the package.
et4U.com
1
VSSQ
NC
NC
NC
NC
VREF
2
NC
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
A12
A11
A8
A6
A4
3
VSS
64 X 4
A
7
VDD
DQ3 B DQ0
NC C NC
DQ2 D DQ1
DQS E QFC
DQM
F
NC
CLK G WE
CKE H RAS
A9 J BA1
A7 K A0
A5 L A2
DataSheet4U.com
VSS M VDD
8
NC
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
1
VSSQ
NC
NC
NC
NC
VREF
2
DQ7
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
A12
A11
A8
A6
A4
3
VSS
DQ6
DQ5
DQ4
DQS
DQM
CLK
CKE
A9
A7
A5
VSS
32 X 8
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ1
DQ2
DQ3
QFC
NC
WE
RAS
BA1
A0
A2
VDD
8
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
DataShee
DataSheetP4Ure.cliomminary
10/01
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.










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Номер в каталогеОписаниеПроизводители
NT5DS64M4AT(NT5DSxxMxAx) 256Mb DDR333/300 SDRAMNanya
Nanya
NT5DS64M4AW(NT5DSxxMxAx) 256Mb DDR333/300 SDRAMNanya
Nanya

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