DataSheet26.com

NT5DS16M8AT PDF даташит

Спецификация NT5DS16M8AT изготовлена ​​​​«Nanya Technology» и имеет функцию, называемую «(NT5DSxxMxAx) 128Mb DDR333/300 SDRAM».

Детали детали

Номер произв NT5DS16M8AT
Описание (NT5DSxxMxAx) 128Mb DDR333/300 SDRAM
Производители Nanya Technology
логотип Nanya Technology логотип 

27 Pages
scroll

No Preview Available !

NT5DS16M8AT Даташит, Описание, Даташиты
www.DataSheet4U.com
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Features
CAS Latency and Frequency
CAS Latency
Maximum Operating Frequency (MHz)*
DDR333
(-6)
DDR300
(-66)
2 133
133
2.5 166
150
* Values are nominal (exact tCK should be used).
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions,
also aligns QFC transitions with CK during Read cycles
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2, 2.5
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 15.6µs Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.5V ± 0.2V
• VDD = 2.5V ± 0.2V
• For -6 speed grade : Support PC2700 modules.
• For -66 speed grade : Support PC2400 modules
• Package :
- 66pin TSOP-II
- 60ball 0.8mmx1.0mm pitch CSP
Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic
Read or Write command are used to select the bank and the
random-access memory containing 134,217,728 bits. It is
starting column location for the burst access.
internally configured as a quad-bank DRAM.
The DDR SDRAM provides for programmable Read or Write
The 128Mb DDR SDRAM uses a double-data-rate arcDhaitteacS- heet4bUur.sctolmengths of 2, 4 or 8 locations. An Auto Precharge func-
ture to achieve high-speed operation. The double data rate
tion may be enabled to provide a self-timed row precharge
DataShee
architecture is essentially a 2n prefetch architecture with an
that is initiated at the end of the burst access.
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 128Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
at the I/O pins.
An auto refresh mode is provided along with a power-saving
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 128Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
DataSheetP4Ure.cliomminary
08/01
DataSheet4 U .com
1
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.









No Preview Available !

NT5DS16M8AT Даташит, Описание, Даташиты
www.DataSheet4U.com
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Pin Configuration - 400mil TSOP II
et4U.com
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
DNU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
DNU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 57
11 56
12 55
13 54
14 53
15 52
16 51
17 50
18 49
19 48
20 47
21 46
22 45
23 DataSheet4U4.c4om
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
66-pin Plastic TSOP-II 400mil
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM*
CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
16Mb x 8
NT5DS16M8AT
32Mb x 4
NT5DS32M4AT
Column Address Table
Organization
32Mb x 4
Column Address
A0-A9, A11
16Mb x 8
A0-A9
*DM is internally loaded to match DQ and DQS identically.
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM*
CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
DataShee
DataSheetP4Ure.cliomminary
08/01
DataSheet4 U .com
2
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.









No Preview Available !

NT5DS16M8AT Даташит, Описание, Даташиты
www.DataSheet4U.com
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Pin Configuration - 60 ball ; 0.8mmx1.0mm Pitch ; CSP
et4U.com
1
VSSQ
NC
NC
NC
NC
VREF
2
NC
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
NC
A11
A8
A6
A4
1
VSSQ
NC
NC
NC
NC
VREF
2
DQ7
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
NC
A11
A8
A6
A4
3
VSS
32 X 4
A
7
VDD
DQ3 B DQ0
NC C NC
DQ2 D DQ1
DQS E DNU
DQM
F
NC
CLK G WE
CKE H RAS
A9 J BA1
A7 K A0
A5 L A2
VSS M VDD
DataSheet4U.com
3
VSS
DQ6
DQ5
DQ4
DQS
DQM
CLK
CKE
A9
A7
A5
VSS
16 X 8
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ1
DQ2
DQ3
DNU
NC
WE
RAS
BA1
A0
A2
VDD
8
NC
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
8
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
DataShee
DataSheetP4Ure.cliomminary
08/01
DataSheet 4 U .com
3
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.










Скачать PDF:

[ NT5DS16M8AT.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
NT5DS16M8AT(NT5DSxxMxAx) 128Mb DDR333/300 SDRAMNanya Technology
Nanya Technology
NT5DS16M8AT(NT5DS16M8AT / NT5DS32M4AT) 128Mb DDR SDRAMNanya Techology
Nanya Techology
NT5DS16M8AW(NT5DSxxMxAx) 128Mb DDR333/300 SDRAMNanya Technology
Nanya Technology

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск