DataSheet26.com

NT5DS16M16BF PDF даташит

Спецификация NT5DS16M16BF изготовлена ​​​​«Nanya Techology» и имеет функцию, называемую «(NT5DSxxMxBx) 256Mb DDR SDRAM».

Детали детали

Номер произв NT5DS16M16BF
Описание (NT5DSxxMxBx) 256Mb DDR SDRAM
Производители Nanya Techology
логотип Nanya Techology логотип 

30 Pages
scroll

No Preview Available !

NT5DS16M16BF Даташит, Описание, Даташиты
www.DataSheet4U.com
NT5DS64M4BT
NT5DS32M8BT
NT5DS16M16BT
NT5DS64M4BF
NT5DS32M8BF
NT5DS16M16BF
256Mb DDR SDRAM
NT5DS64M4BS
NT5DS32M8BS
NT5DS16M16BS
NT5DS64M4BG
NT5DS32M8BG
NT5DS16M16BG
Features
CAS Latency and Frequency
CAS
Latency
3
Maximum Operating Frequency (MHz)
DDR400B
(-5T)
200
2.5 166
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2.5, 3
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8µs Maximum Average Periodic Refresh Interval
• SSTL_2 compatible I/O interface
• VDDQ = 2.6V ± 0.1V
• VDD = 2.6V ± 0.1V
• Lead-free and Halogen-free product available
Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic
tion may be enabled to provide a self-timed row precharge
random-access memory containing 268,435,456 bits. It is
that is initiated at the end of the burst access.
internally configured as a quad-bank DRAM.
As with standard SDRAMs, the pipelined, multibank architec-
The 256Mb DDR SDRAM uses a double-data-rate architec-
ture of DDR SDRAMs allows for concurrent operation,
ture to achieve high-speed operation. The double data rate
thereby providing high effective bandwidth by hiding row pre-
architecture is essentially a 2n prefetch architecture with an
charge and activation time.
ianttethrefaIc/eOdpeinssig.nAedsintoglterarnesafderotrwworditaetaacwcoersdssfopretrhcelo2c5Dk6acMytabcSleheet4AUn.acuotmo refresh mode is provided along with a power-saving DataShee
DDR SDRAM effectively consists of a single 2n-bit wide, one Power Down mode. All inputs are compatible with the JEDEC
clock cycle data transfer at the internal DRAM core and two
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
corresponding n-bit wide, one-half-clock-cycle data transfers patible.
at the I/O pins.
The functionality described and the timing specifications
A bidirectional data strobe (DQS) is transmitted externally,
included in this data sheet are for the DLL Enabled mode
along with data, for use in data capture at the receiver. DQS of operation.
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
DataSheetR4UE.Vco1m.3
06/2003
1
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
DataSheet4 U .com









No Preview Available !

NT5DS16M16BF Даташит, Описание, Даташиты
www.DataSheet4U.com
NT5DS64M4BT
NT5DS32M8BT
NT5DS16M16BT
NT5DS64M4BF
NT5DS32M8BF
NT5DS16M16BF
256Mb DDR SDRAM
NT5DS64M4BS
NT5DS32M8BS
NT5DS16M16BS
NT5DS64M4BG
NT5DS32M8BG
NT5DS16M16BG
Pin Configuration - 400mil TSOP II (x4 / x8 / x16)
et4U.com
VD D
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VD D
NU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
V SSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VD D
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NU
LDM*
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 57
11 56
12 55
13 54
14 53
15 52
16 51
17 50
18 49
19 48
20 47
21 46
22 45
2D3 ataSheet4U.com44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
66-pin Plastic TSOP-II 400mil
V SS
DQ15
V SSQ
DQ14
DQ13
V DDQ
DQ12
DQ11
V SSQ
DQ10
DQ9
V DDQ
DQ8
NC
V SSQ
UDQS
NC
VREF
V SS
UDM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V SS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V SS
16Mb x 16
32Mb x 8
64Mb x 4
Column Address Table
Organization
64Mb x 4
Column Address
A0-A9, A11
32Mb x 8
A0-A9
16Mb x 16
A0-A8
*DM is internally loaded to match DQ and DQS identically.
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V SS
DataShee
DataSheetR4UE.Vco1m.3
06/2003
DataSheet4 U .com
2
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.









No Preview Available !

NT5DS16M16BF Даташит, Описание, Даташиты
www.DataSheet4U.com
NT5DS64M4BT
NT5DS32M8BT
NT5DS16M16BT
NT5DS64M4BF
NT5DS32M8BF
NT5DS16M16BF
256Mb DDR SDRAM
NT5DS64M4BS
NT5DS32M8BS
NT5DS16M16BS
NT5DS64M4BG
NT5DS32M8BG
NT5DS16M16BG
Pin Configuration - 60 balls 0.8mmx1.0mm Pitch CSP Package
<Top View >
See the balls through the package.
et4U.com
1
VSSQ
NC
NC
NC
NC
VREF
2
NC
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
A12
A11
A8
A6
A4
3
VSS
64 X 4
A
7
VDD
DQ3 B DQ0
NC C NC
DQ2 D DQ1
DQS E QFC
DQM
F
NC
CLK G WE
CKE H RAS
A9 J BA1
A7 K A0
A5DataSheLet4U.comA2
VSS M VDD
8
NC
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
1
VSSQ
NC
NC
NC
NC
VREF
2
DQ7
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
A12
A11
A8
A6
A4
3
VSS
DQ6
DQ5
DQ4
DQS
DQM
CLK
CKE
A9
A7
A5
VSS
32 X 8
A
B
C
D
E
F
G
H
J
K
L
M
7
VDD
DQ1
DQ2
DQ3
QFC
NC
WE
RAS
BA1
A0
A2
VDD
8
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
9
VDDQ
NC
NC
NC
NC
NC
DataShee
DataSheetR4UE.Vco1m.3
06/2003
DataSheet 4 U .com
3
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.










Скачать PDF:

[ NT5DS16M16BF.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
NT5DS16M16BF(NT5DSxxMxBx) 256Mb DDR SDRAMNanya Techology
Nanya Techology
NT5DS16M16BF(NT5DSxxMxBx) 256Mb DDR SDRAMNanya Techology
Nanya Techology
NT5DS16M16BG(NT5DSxxMxBx) 256Mb DDR SDRAMNanya Techology
Nanya Techology
NT5DS16M16BS(NT5DSxxMxBx) 256Mb DDR SDRAMNanya Techology
Nanya Techology

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск