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NT5DS64M4CT PDF даташит

Спецификация NT5DS64M4CT изготовлена ​​​​«Nanya Techology» и имеет функцию, называемую «(NT5DSxxMxCx) 256Mb SDRAM».

Детали детали

Номер произв NT5DS64M4CT
Описание (NT5DSxxMxCx) 256Mb SDRAM
Производители Nanya Techology
логотип Nanya Techology логотип 

70 Pages
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NT5DS64M4CT Даташит, Описание, Даташиты
www.DataSheet4U.com
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
NT5DS16M16CG
Features
CAS Latency and Frequency
CAS
Latency
Maximum Operating Frequency
(MHz)
DDR400
(5T)
DDR333
(6K/6KL)
2-
133
2.5 166
166
3 200
-
• DDR 256M bit, die C, based on 110nm design rules
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2/2.5(DDR333) , 2.5/3(DDR400)
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 7.8ms Maximum Average Periodic Refresh Interval
• 2.5V (SSTL_2 compatible) I/O
• VDD = VDDQ = 2.5V ± 0.2V (DDR333)
• VDD = VDDQ = 2.6V ± 0.1V (DDR400)
• Available in Halogen and Lead Free packaging
Description
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT,
Read or Write command are used to select the bank and the
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS, and
starting column location for the burst access.
NT5DS16M16CG are die C of 256Mb SDRAM devices based
using DDR interface. They are all based on Nanya’s 110 nm The DDR SDRAM provides for programmable Read or Write
design process.
burst lengths of 2, 4, or 8 locations. An Auto Precharge func-
The
256Mb
DDR
SDRAM
uses
a
double-data-rate
arcDhaitteacS- heet4tthiUoan.tcmiosmainyitbiaeteednaabt ltehde
to provide a self-timed row
end of the burst access.
precharge
DataShee
ture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 256Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
An auto refresh mode is provided along with a power-saving
Power Down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
A bidirectional data strobe (DQS) is transmitted externally,
patible.
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
Writes.
The 256Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
DataSheetR4UE.Vco1m.2
Nov 10, 2005
DataSheet4 U .com
1
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.









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NT5DS64M4CT Даташит, Описание, Даташиты
www.DataSheet4U.com
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
NT5DS16M16CG
256Mb DDR SDRAM
Ordering Information
Org. Part Number
Package
Speed
Clock (MHz) CL-tRCD-tRP
Comments
64M x 4
NT5DS64M4CT-5T
NT5DS64M4CT-6K
TSOP2
200 3-3-3
166 2.5-3-3
DDR400
DDR333
NT5DS32M8CT-5T
32M x 8
NT5DS32M8CT-6K/6KL
TSOP2
200 3-3-3
166 2.5-3-3
DDR400
DDR333
16M x 16
NT5DS16M16CT-5T
NT5DS16M16CT-6K
TSOP2
200 3-3-3
166 2.5-3-3
DDR400
DDR333
64M x 4
NT5DS64M4CS-5T
NT5DS64M4CS-6K
TSOP2
Green Packing
200 3-3-3
166 2.5-3-3
DDR400
DDR333
32M x 8
NT5DS32M8CS-5T
NT5DS32M8CS-6K
TSOP2
Green Packing
200 3-3-3
166 2.5-3-3
DDR400
DDR333
16M x 16
NT5DS16M16CS-5T
NT5DS16M16CS-6K
TSOP2
Green Packing
200 3-3-3
166 2.5-3-3
DDR400
DDR333
NT5DS16M16CG-5T
16M x 16
wBGA
200 3-3-3
NT5DS16M16CG-6K
Green Package
166
2.5-3-3
DDR400
DDR333
Note:
et4U.com
1. At the present time, there are no plans to support DDRDSaDtRaASMhseweitth4Uth.ecQoFmC function. All reference to QFC
are for information only
Green Packing are Lead and Halogen free products
DataShee
DataSheetR4UE.Vco1m.2
Nov 10, 2005
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.









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NT5DS64M4CT Даташит, Описание, Даташиты
www.DataSheet4U.com
NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT
NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS
NT5DS16M16CG
256Mb DDR SDRAM
Pin Configuration - 400mil TSOP II (x4 / x8 / x16)
et4U.com
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
NU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NU
LDM*
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 57
11 56
12 55
13 54
14 53
15 52
16 51
17 50
18 49
19 48
20 47
21 46
22 45
2D3 ataSheet4U.com44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
66-pin Plastic TSOP-II 400mil
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
16Mb x 16
32Mb x 8
64Mb x 4
Column Address Table
Organization
64Mb x 4
Column Address
A0-A9, A11
32Mb x 8
A0-A9
16Mb x 16
A0-A8
*DM is internally loaded to match DQ and DQS identically.
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM*
CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
DataShee
DataSheetR4UE.Vco1m.2
Nov 10, 2005
DataSheet4 U .com
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.










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Номер в каталогеОписаниеПроизводители
NT5DS64M4CS(NT5DSxxMxCx) 256Mb SDRAMNanya Techology
Nanya Techology
NT5DS64M4CT(NT5DSxxMxCx) 256Mb SDRAMNanya Techology
Nanya Techology

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