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NT5DS16M8AT PDF даташит

Спецификация NT5DS16M8AT изготовлена ​​​​«Nanya Techology» и имеет функцию, называемую «(NT5DS16M8AT / NT5DS32M4AT) 128Mb DDR SDRAM».

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Номер произв NT5DS16M8AT
Описание (NT5DS16M8AT / NT5DS32M4AT) 128Mb DDR SDRAM
Производители Nanya Techology
логотип Nanya Techology логотип 

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NT5DS16M8AT Даташит, Описание, Даташиты
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NT5DS32M4AT
NT5DS16M8AT
128Mb Double Data Rate SDRAM
Features
CAS Latency and Frequency
CAS Latency
Maximum Operating Frequency (MHz)*
DDR266A
(-7K)
DDR266B
(-75B)
DDR200
(-8B)
2 133 100
2.5 143 133
* Values are nominal (exact tCK should be used).
100
125
• Double data rate architecture: two data transfers per
clock cycle
• Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
• DQS is edge-aligned with data for reads and is center-
aligned with data for writes
• Differential clock inputs (CK and CK)
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• DLL aligns DQ and DQS transitions with CK transitions,
also aligns QFC transitions with CK during Read cycles
• Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
• Burst lengths: 2, 4, or 8
• CAS Latency: 2, 2.5
• Auto Precharge option for each burst access
• Auto Refresh and Self Refresh Modes
• 15.6µs Maximum Average Periodic Refresh
Interval
• Supports tRAS lockout feature
• 2.5V (SSTL_2 compatible) I/O
• VDDQ = 2.5V ± 0.2V
• VDD = 2.5V ± 0.2V
• -7K parts support PC2100 modules.
-75B parts support PC2100 modules
-8B parts support PC1600 modules
Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic
Read or Write command are used to select the bank and the
random-access memory containing 134,217,728 bits. It is
starting column location for the burst access.
internally configured as a quad-bank DRAM.
The DDR SDRAM provides for programmable Read or Write
The 128Mb DDR SDRAM uses a double-data-rate arcDhaitetacS- heet4bUur.sctolmengths of 2, 4 or 8 locations. An Auto Precharge func-
ture to achieve high-speed operation. The double data rate
tion may be enabled to provide a self-timed row precharge
DataShee
architecture is essentially a 2n prefetch architecture with an
that is initiated at the end of the burst access.
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 128Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
at the I/O pins.
An auto refresh mode is provided along with a power-saving
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
Note: The functionality described and the timing specifi-
cations included in this data sheet are for the DLL
Enabled mode of operation.
The 128Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.









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NT5DS32M4AT
NT5DS16M8AT
128Mb Double Data Rate SDRAM
Pin Configuration - 128Mb DDR SDRAM (x4 / x8)
et4U.com
VD D
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
NC
VD D
DNU, QFC +
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V DD
V DD
DQ0
VDDQ
NC
DQ1
V SSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
NC
VDD
DNU, QFC+
NC
WE
CAS
RAS
CS
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V DD
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 57
11 56
12 55
13 54
14 53
15 52
16 51
17 50
18 49
19 48
20 47
21 46
22 45
23 DataSheet4U4.c4om
24 43
25 42
26 41
27 40
28 39
29 38
30 3 7
31 36
32 35
33 34
66-pin Plastic TSOP-II 400mil
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM*
CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
NC
VR E F
VSS
DM*
CK
CK
CKE
NC
NC
A11
A9
A8
A7
A6
A5
A4
VSS
16Mb x 8
NT5DS16M8AT
32Mb x 4
NT5DS32M4AT
Column Address Table
Organization
32Mb x 4
16Mb x 8
Column Address
A0-A9, A11
A0-A9
*DM is internally loaded to match DQ and DQS identically.
+QFC is an optional feature and must be specified via p/n when ordering devices.
DataShee
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.









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NT5DS16M8AT Даташит, Описание, Даташиты
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NT5DS32M4AT
NT5DS16M8AT
128Mb Double Data Rate SDRAM
Input/Output Functional Description
Symbol
CK, CK
CKE
CS
RAS, CAS , WE
DM
BA0, BA1
et4U.com
A0 - A11
DQ
DQS
QFC
NC
DNU
VDDQ
VSSQ
VDD
VSS
VREF
Type
Input
Input
Input
Input
Input
Input
Input
Input/Output
Input/Output
Output
Supply
Supply
Supply
Supply
Supply
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during self refresh.
Chip Select: All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading.Dur-
ing a Read, DM can be driven high, low, or floated.
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. BA0 and BA1 also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.
Address Inputs: Provide the row address for Active commands, and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,
the bank
Register
SisestecloeDmctmaedtaanbSdy.hBeAe0,t4BUA1.c. Tohme
address
inputs
also
provide
the
op-code
during
a
Mode
DataShee
Data Input/Output: Data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered
in write data. Used to capture write data.
FET control : Optional. Output during every Read and Write access. Is provided to control isola-
tion switches on modules. Open drain output. Pullup resistor connected to VDDQ must be supplied
at second level of assembly.
No Connect: No internal electrical connection is present.
Electrical connection is present. Should not be connected at second level of assembly.
DQ Power Supply: 2.5V ± 0.2V.
DQ Ground
Power Supply: 2.5V ± 0.2V.
Ground
SSTL_2 reference voltage: (VDDQ / 2) ± 1%.
DataSheetR4UE.Vco1m.0
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DataSheet4 U .com
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© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.










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