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SDA9290-5 PDF даташит

Спецификация SDA9290-5 изготовлена ​​​​«Siemens Semiconductor» и имеет функцию, называемую «Picture Processor».

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Номер произв SDA9290-5
Описание Picture Processor
Производители Siemens Semiconductor
логотип Siemens Semiconductor логотип 

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Picture Processor
Preliminary Data
Features
q Noise and cross color reduction by field - or frame
recursive filtering
q 3 adjustments: 4-dB-, 7-dB- or 12-dB reduction
q Automatic adaption to signal quality during vertical
blanking
q Pixel adaptive movement detection
q Split screen modes for demonstration purposes
q Multi-picture facilities
q Picture decimation using vertical filtering
q 8 programmable grey levels for framing
q 4:1:1 and 4:2:2 (Y:U:V) compatibility
q 8-bit word size for all components
SDA 9290-5
NMOS IC
P-LCC-68-1
Type
SDA 9290-5
Ordering Code
Q67100-H5088
Package
P-LCC-68-1 (SMD)
Functional Description
The NMOS device SDA 9290-5 is a picture processor and belongs to a family of devices forming
an extended third-generation digital TV signal-processing system for enhanced picture quality with
special functions (Featurebox). Besides the Picture Processor (PP) that is described here, the
system consists of a field memory (at least three triple-port, 1-Mbit generation TV Sequential-
Access Memory devices (SDA 9251 X), a Memory Sync Controller (MSC SDA 9220-5) and a Video
D/A converter (SDA 9094-5). A block diagram of the Featurebox is shown in figure 1.
The Picture Processor SDA 9290-5 is a follow-on development of the Picture Processor SDA 9090
from the second-generation Featurebox and permits further picture improvement by reducing the
video noise and cross-color interference. The SDA 9290-5 can be set independently at the picture-
signal input and output via the two pins FSBQ/FSI to the 4:1:1 and 4:2:2 formats. A 4:1:1
Featurebox (3 TV-SAMs) can therefore be operated with 4:2:2 input signals as well.
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SDA 9290-5
The necessary decimation and interpolation operations are activated automatically when the format
is set. Together with a corresponding Memory Sync Controller (SDA 9220) it enables functions like
multi-picture, tuner scanning, picture-in-still and still-in-picture. The different modes can be
activated by a microcontroller on the I2C Bus interface (slave receiver). The I2C Bus address for
accessing the device is
00101010
Circuit Description
The core of the picture processor (see block diagram) is formed of the Image-lmproving Processor
(IIP) and the Multi-Picture Processor (MPP). The IIP is responsible for noise and cross-color
reduction, while the MPP together with the new Memory Sync Controller implements the functions
multi-picture, tuner scanning, picture-in-still and still-in-picture.
Image-lmproving Processor
The signal inputs Yl0-YI7 and UVI0-UVI7 and the back-channel signal inputs YB0-YB7 and UVB0-
UVB7 picture data with 12 bits in quasi-parallel format (4:1:1) and with 16 bits in parallel format
(4:2:2). The clock rate for both signals is 13.5 MHz. For signal processing in the IIP and MPP the
chrominance bit levels have to be separated in the case of the quasi parallel format by
demultiplexers DEMUXS and DEMUXR, these being largely identical in design.
A reduction in video noise is achieved by correlating the picture contents of two successive fields,
the non-correlated components (noise) being attenuated by the digital filter. To achieve this, the
instantaneous digital picture signal on the outputs of the demultiplexer DEMUXS and the picture
signal delayed by a field interval on the outputs of the back-channel demultiplexer DEMUXR are fed
to the IIP and combined.
The signal-to-noise ratio (S/N) unit detects the noise components of the input signals and the
movement detector uses this information to select an appropriate set of parameters with filter
coefficients and thresholds for the comparators. For this purpose the luminance signal is assigned
to one of three classes according to its S/N ratio, with each class defining a different degree of
maximum noise reduction. The limits between the middle class and the upper and lower classes
can be programmed by the I2C Bus registers R1 and R2 with the values for the thresholds SU and
SL. When the picture signals come from a video cassette recorder, the adaptation on the S/N ratio
of the input signal should be disabled by I2L Bus register R0, VCR bit D2.
Measurement of the signal-to-noise ratio in the automatic mode has been advanced from line 7 to
line 6 in order to avoid conflicts with future text and data services.
The degree of noise reduction for the luminance and chrominance signals can be varied between
0 dB and 12 dB by selecting the appropriate filter coefficients.
A picture signal with reduced noise and cross-color appears on the output of the IIP for further
processing. The signal will be forwarded via blocks MUXI and MUXO to the picture memories
through the outputs (YQ0-YQ7 and UVQO-UVQ7 respectively).
The coefficients of the selected class are controlled by the movement detector as a function of
pixels to prevent artifacts (loss of focus) in moving parts of the picture.
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SDA 9290-5
Multi-Picture Processor
Signals are processed in the 4:1:1 format. The vertical-decimation line memory now operates with
208 (formerly 216) pixels per line to adapt the 1/9th picture format to the new picture memory with
TV-SAMs. Gray frame generation is similarly affected by this change in pixel value.
The signal processing in the decimation filter of the MPP reduces the picture to approximately 1/9th
of its original size. This produces a basis for new features, the full implementation of which calls for
a matching MSC (SDA 9220).
Figure 5 shows how the screen is divided up. The following modes can be implemented with the
MPP:
1. Multi-Picture (automatic)
Fields are extracted from a sequence of movements at fixed intervals, reduced and reproduced
on the screen as a sequence of stills. At one position it is possible to show a moving picture.
2. Multi-Picture (manual)
This differs from the above in that the viewer can determine at the push of a button what phases
of movement are to be stored.
3. Multi-Picture (tuner scanning)
The pictures of the sequence of stills are derived from the different TV channels and give an
overview of the programs on offer. In this mode the picture memory is operated with a crystal-
controlled clock to ensure that the picture remains stable when switching from one channel to
another.
4. Still-in-Picture
A field is extracted from the on-going program, reduced and inserted as a still in the master
channel.
5. Picture-in-Still
The on-going program is inserted as a reduced-size moving picture in a still.
The framing block that follows the decimation filter in the MPP permits frames to be inserted in order
to border the reduced-size pictures on the screen. The brightness of the framing can be varied in
eight steps by the I2C Bus.
The format conversion produced in the demultiplexers for signal processing in the IIP and MPP is
reversed again in the multiplexer MUXO. The picture signal appears again in quasi-parallel format
or parallel format on the output of the MUXO block. The inputs of the TV-SAMs are directly driven
by the sixteen outputs YQ0-YQ7 and UVQ0-UVQ7.
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Номер в каталогеОписаниеПроизводители
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