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PDF NTMD3P03R2 Data sheet ( Hoja de datos )
| Número de pieza | NTMD3P03R2 | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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NTMD3P03R2
Power MOSFET
−3.05 Amps, −30 Volts
Dual P−Channel SO−8
Features
• High Efficiency Components in a Dual SO−8 Package
• High Density Power MOSFET with Low RDS(on)
• Miniature SO−8 Surface Mount Package − Saves Board Space
• Diode Exhibits High Speed with Soft Recovery
• IDSS Specified at Elevated Temperature
• Avalanche Energy Specified
• Mounting Information for the SO−8 Package is Provided
Applications
• DC−DC Converters
• Low Voltage Motor Control
• Power Management in Portable and Battery−Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular & Cordless Telephones
MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance −
Junction−to−Ambient (Note 1)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4)
Thermal Resistance −
Junction−to−Ambient (Note 2)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4)
Thermal Resistance −
Junction−to−Ambient (Note 3)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ 25°C
Continuous Drain Current @ 70°C
Pulsed Drain Current (Note 4)
Operating and Storage
Temperature Range
VDSS
VGS
RθJA
PD
ID
ID
IDM
RθJA
PD
ID
ID
IDM
RθJA
PD
ID
ID
IDM
TJ, Tstg
−30 V
±20 V
171
0.73
−2.34
−1.87
−8.0
°C/W
W
A
A
A
100
1.25
−3.05
−2.44
−12
°C/W
W
A
A
A
62.5
2.0
−3.86
−3.1
−15
−55 to
+150
°C/W
W
A
A
A
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = −30 Vdc, VGS = −4.5 Vdc, Peak
IL = −7.5 Apk, L = 5 mH, RG = 25 Ω)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
EAS
TL
140 mJ
260 °C
1. Minimum FR−4 or G−10 PCB, t = Steady State.
2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single
sided), t = steady state.
3. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single
sided), t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
http://onsemi.com
VDSS
−30 V
RDS(ON) TYP
85 mΩ @ −10 V
ID MAX
−3.05 A
P−Channel
D
G
8
1
SO−8
CASE 751
STYLE 11
S
MARKING
DIAGRAM
ED3P03
LYWW
ED3P03
L
Y
WW
= Device Code
= Assembly Location
= Year
= Work Week
PIN ASSIGNMENT
Source−1
Gate−1
Source−2
Gate−2
18
27
36
45
Top View
Drain−1
Drain−1
Drain−2
Drain−2
ORDERING INFORMATION
Device
Package
Shipping†
NTMD3P03R2
SO−8
2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2004
May, 2004 − Rev. 1
1
Publication Order Number:
NTMD3P03R2/D
1 page  
NTMD3P03R2
100
VGS = 12 V
SINGLE PULSE
TC = 25°C
10
1.0 dc
1.0 ms
10 ms
0.1
0.01
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1.0
10
100
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 13. Maximum Rated Forward Biased
Safe Operating Area
IS
tp
di/dt
trr
ta tb
0.25 IS
IS
TIME
Figure 14. Diode Reverse Recovery Waveform
1.0
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
1E−03
0.01
Single Pulse
1E−02
Chip
Normalized to RθJA at Steady State (1″ pad)
Junction 2.32 Ω 18.5 Ω 50.9 Ω 37.1 Ω 56.8 Ω
24.4 Ω
1E−01
0.0014 F 0.0073 F 0.022 F 0.105 F
1E+00
t, TIME (s)
1E+01
0.484 F
1E+02
3.68 F
Ambient
1E+03
Figure 15. FET Thermal Response
http://onsemi.com
5
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| PDF Descargar | [ Datasheet NTMD3P03R2.PDF ] | |
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