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OXMPCI952 PDF даташит

Спецификация OXMPCI952 изготовлена ​​​​«Oxford Semiconductor» и имеет функцию, называемую «Integrated High Performance Dual UARTs».

Детали детали

Номер произв OXMPCI952
Описание Integrated High Performance Dual UARTs
Производители Oxford Semiconductor
логотип Oxford Semiconductor логотип 

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OXMPCI952 Даташит, Описание, Даташиты
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FEATURES
Dual 16C950 High performance UART channels
8-bit Pass-through Local Bus (PCI Bridge)
IEEE1284 Compliant SPP/EPP/ECP parallel port (with
external transceiver)
Efficient 32-bit, 33MHz, Multi-function target-only PCI
controller, fully compliant to PCI Local Bus specification 3.0,
and PCI Power Management Specification 1.1
PCI and miniPCI Modes (with CLKRUN# and PME#
generation in the D3cold state, in miniPCI mode)
UARTs fully software compatible with 16C550-type devices.
UART operation up to 60 MHz via external clock source. Up
to 20MHz with the crystal oscillator.
Baud rates up to 60Mbps in external 1x clock mode and
15Mbps in asynchronous mode.
128-byte deep FIFO per transmitter and receiver
Flexible clock prescaler, from 1 to 31.875
Automated in-band flow control using programmable
Xon/Xoff in both directions
Automated out-of-band flow control using CTS#/RTS#
and/or DSR#/DTR#
DESCRIPTION
The OXmPCI952 is a single chip solution for PCI and mini-
PCI based serial and parallel expansion add-in cards. It is
a dual function PCI device, where function 0 offers two
ultra-high performance OX16C950 UARTs, and function 1
is configurable either as an 8-bit Local Bus or a bi-
directional parallel port.
Each UART channel in the OXmPCI952 is the fastest
available PC-compatible UART, offering data rates up to
15Mbps and 128-byte deep transmitter and receiver FIFOs.
The deep FIFOs reduce CPU overhead and allow
utilisation of higher data rates. Each UART channel is
software compatible with the widely used industry-standard
16C550 devices (and compatibles), as well as the
OX16C95x family of high performance UARTs. In addition
to increased performance and FIFO size, the UARTs also
provide the full set of OX16C95x enhanced features
including automated in-band flow control, readable FIFO
levels etc.
To enhance device driver efficiency and reduce interrupt
latency, internal UARTs have multi-port features such as
shadowed FIFO fill levels, a global interrupt source register
and Good-Data Status, readable in four adjacent DWORD
OXmPCI952 DATA SHEET
Integrated High Performance Dual UARTs,
8-bit Local Bus/Parallel Port.
3.3v PCI/miniPCI interface.
Arbitrary trigger levels for receiver and transmitter FIFO
interrupts and automatic in-band and out-of-band flow
control
Infra-red (IrDA) receiver and transmitter operation
9-bit data framing, as well as 5,6,7 and 8 bits
Detection of bad data in the receiver FIFO
Global Interrupt Status and readable FIFO levels to facilitate
implementation of efficient device drivers.
Local registers to provide status/control of device functions.
11 multi-purpose I/O pins, which can be configured as input
interrupt pins or ‘wake-up’.
Auto-detection of a wide range of MicrowireTM compatible
EEPROMs, to configure device parameters.
Function access, to pre-configure each function prior to
handover to generic device drivers.
Operation via IO or memory mapping.
3.3V operation (5v tolerance on selected I/Os)
Extended Operating Temp. Range : -40C to 105C
160-pin LQFP/176-pin BGA package
registers visible to logical functions in I/O space and
memory space.
Expansion of serial cards beyond two channels is possible
using the 8-bit pass-through Local Bus function. The
addressable space can be increased up to 256 bytes, and
divided into four chip-select regions. This flexible
expansion scheme caters for cards with up to 18 serial
ports using external 16C950, 16C952, 16C954 or
compatible devices, or composite applications such as
combined serial and parallel port expansion cards.
The parallel port is an IEEE 1284 compliant SPP/EPP/
ECP parallel port that fully supports the existing Centronics
interface. The parallel port can be enabled in place of the
Local Bus. An external bus transceiver is required for 5V
parallel port operation.
The configuration register values are programmed using an
external MicrowireTM compatible serial EEPROM. This
EEPROM can also be used to provide function access, to
pre-configure each UART into enhanced modes or pre-
configure devices on the local bus/parallel port, prior to any
PCI configuration accesses and before control is handed to
(generic) device drivers.
Oxford Semiconductor Ltd.
External—Free Release
© Oxford Semiconductor 2005
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
OXmPCI952 DataSheet DS-0020 – June 2005
Tel: +44 (0)1235 824900 Fax: +44(0)1235 821141









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OXMPCI952 Даташит, Описание, Даташиты
OXFORD SEMICONDUCTOR LTD.
OXmPCI952
REVISION HISTORY
REV
1.0
Jan 2005
Jun 2005
DATE
05/09/2003
25/1/2005
8/6/2005
REASON FOR CHANGE / SUMMARY OF CHANGE
Initial DataSheet
Revisions for additional 176-pin BGA layout
Revision for additional green order code for 160-pin LQFP layout
DS-0020 Jun 05
Page 2









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OXMPCI952 Даташит, Описание, Даташиты
OXFORD SEMICONDUCTOR LTD.
OXmPCI952
TABLE OF CONTENTS
1 BLOCK DIAGRAM ................................................................................................................................ 8
2 PIN INFORMATION—160-PIN LQFP .................................................................................................... 9
2.1 PINOUTS............................................................................................................................................................................. 9
2.2 PIN DESCRIPTIONS......................................................................................................................................................... 10
3 PIN INFORMATION—176-PIN BGA.................................................................................................... 16
3.1 PINOUTS........................................................................................................................................................................... 16
3.2 PIN DESCRIPTIONS......................................................................................................................................................... 17
4 CONFIGURATION & OPERATION ..................................................................................................... 22
5 PCI TARGET CONTROLLER.............................................................................................................. 23
5.1 OPERATION ..................................................................................................................................................................... 23
5.2 CONFIGURATION SPACE ............................................................................................................................................... 23
5.2.1 PCI CONFIGURATION SPACE REGISTER MAP........................................................................................................ 24
5.3 ACCESSING LOGICAL FUNCTIONS .............................................................................................................................. 26
5.3.1 PCI ACCESS TO INTERNAL UARTS........................................................................................................................... 26
5.3.2 PCI ACCESS TO 8-BIT LOCAL BUS............................................................................................................................ 27
5.3.3 PCI ACCESS TO PARALLEL PORT ............................................................................................................................ 28
5.4 ACCESSING LOCAL CONFIGURATION REGISTERS................................................................................................... 29
5.4.1 LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ........................................................ 29
5.4.2 MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................ 30
5.4.3 LOCAL BUS TIMING PARAMETER REGISTER 1 ‘LT1’ (OFFSET 0X08): .................................................................. 32
5.4.4 LOCAL BUS TIMING PARAMETER REGISTER 2 ‘LT2’ (OFFSET 0X0C): ................................................................. 33
5.4.5 UART RECEIVER FIFO LEVELS ‘URL’ (OFFSET 0X10)............................................................................................. 35
5.4.6 UART TRANSMITTER FIFO LEVELS ‘UTL’ (OFFSET 0X14)...................................................................................... 35
5.4.7 UART INTERRUPT SOURCE REGISTER ‘UIS’ (OFFSET 0X18)............................................................................... 35
5.4.8 GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X1C) ................................................ 36
5.5 PCI INTERRUPTS............................................................................................................................................................. 38
5.6 POWER MANAGEMENT .................................................................................................................................................. 39
5.6.1 POWER MANAGEMENT OF FUNCTION 0 ................................................................................................................. 39
5.6.2 POWER MANAGEMENT OF FUNCTION 1 ................................................................................................................. 40
5.7 MINIPCI SUPPORT........................................................................................................................................................... 42
5.8 DEVICE DRIVERS ............................................................................................................................................................ 46
6 INTERNAL OX16C950 UARTS ........................................................................................................... 47
6.1 OPERATION – MODE SELECTION ................................................................................................................................. 47
6.1.1 450 MODE..................................................................................................................................................................... 47
6.1.2 550 MODE..................................................................................................................................................................... 47
6.1.3 EXTENDED 550 MODE ................................................................................................................................................ 47
6.1.4 750 MODE..................................................................................................................................................................... 47
6.1.5 650 MODE..................................................................................................................................................................... 47
6.1.6 950 MODE..................................................................................................................................................................... 48
6.2 REGISTER DESCRIPTION TABLES ............................................................................................................................... 49
6.3 RESET CONFIGURATION ............................................................................................................................................... 53
6.3.1 HARDWARE RESET .................................................................................................................................................... 53
6.3.2 SOFTWARE RESET ..................................................................................................................................................... 53
6.4 TRANSMITTER AND RECEIVER FIFOS ......................................................................................................................... 54
6.4.1 FIFO CONTROL REGISTER ‘FCR’ .............................................................................................................................. 54
6.5 LINE CONTROL & STATUS............................................................................................................................................. 55
6.5.1 FALSE START BIT DETECTION.................................................................................................................................. 55
6.5.2 LINE CONTROL REGISTER ‘LCR’............................................................................................................................... 55
6.5.3 LINE STATUS REGISTER ‘LSR’ .................................................................................................................................. 56
DS-0020 Jun 05
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