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PDF NB4L339 Data sheet ( Hoja de datos )
| Número de pieza | NB4L339 | |
| Descripción | 2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan-Out Buffer | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NB4L339
2.5 V / 3.3 V Differential 2:1
Clock IN to Differential
LVPECL Clock Generator /
Divider / Fan-Out Buffer
Multi−Level Inputs w/ Internal Termination
Description
The NB4L339 is a multi−function Clock generator featuring a 2:1
Clock multiplexer front end and simultaneously outputs a selection of
four different divide ratios from its four divider blocks; ÷1/÷2/÷4/÷8.
One divide block has a choice of ÷1 or ÷ 2.
The output of each divider block is fanned−out to two identical
differential LVPECL copies of the selected clock. All outputs provide
standard LVPECL voltage levels when externally terminated with a
50−ohm resistor to VCC − 2 V.
The differential Clock inputs incorporate internal 50−W termination
resistors and will accept LVPECL, CML or LVDS logic levels.
The common Output Enable pin (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the internal clock
is in the LOW state. This avoids any chance of generating a runt clock
pulse on the internal clock when the device is enabled/disabled as can
happen with an asynchronous control. An internal runt pulse could
lead to losing synchronization between the internal divider stages. The
internal enable flip−flop is clocked on the falling edge of the input
clock. Therefore, all associated specification limits are referenced to
the negative edge of the clock input.
This device is housed in a 5x5 mm 32 pin QFN package.
Features
• Maximum Input/Output Clock Frequency > 700 MHz
• Low Skew LVPECL Outputs, 15 ps typical
• 1 ns Typical Propagation Delay
• 150 ps Typical Rise and Fall Times
• 0.15 ps Typical RMS Phase Jitter
• 0.5 ps Typical RMS Random Clock Period Jitter
• LVPECL, CML or LVDS Input Compatible
• Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V
• LVPECL Output Level; 750 mV Peak−to−Peak, Typical
• Internal 50−W Input Termination Provided
• Synchronous Output Enable/Disable
• Asynchronous Master Reset
• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
• −40°C to 85°C Ambient Operating Temperature
• 32−Pin QFN, 5 mm x 5 mm
• This is a Pb−Free Device
© Semiconductor Components Industries, LLC, 2012
September, 2012 − Rev. 3
1
http://onsemi.com
MARKING
DIAGRAM
1 32
QFN32
MN SUFFIX
CASE 488AM
1
NB4L339
AWLYYWWG
G
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
Figure 1. Simplified Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information on page 11 of
this data sheet.
Publication Order Number:
NB4L339/D
1 page  
NB4L339
Table 7. DC CHARACTERISTICS, CLOCK Inputs, LVPECL Outputs
VCC = 2.375 V to 3.6 V, VEE = 0 V, TA = −40°C to +85°C (Note 5)
Symbol
Characteristic
Min Typ Max Unit
IEE Power Supply Current (Inputs and Outputs Open)
LVPECL Outputs (Note 4)
58 70 90 mA
VOH Output HIGH Voltage
VOL Output LOW Voltage
Differential Input Driven Single−Ended (see Figures 6 & 8)
VCC = 3.3 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 2.5 V
VCC − 1135
2155
1355
VCC − 1935
1355
555
VCC − 1020
2280
1480
VCC − 1770
1530
730
VCC − 760
2540
1740
VCC − 1560
1740
940
mV
mV
Vth Input Threshold Reference Voltage Range (Note 6)
VIH Single−ended Input HIGH Voltage
VIL Single−ended Input LOW Voltage
VISE
Single−ended Input Voltage (VIH − VIL)
Differential Inputs Driven Differentially (see Figures 7 & 9)
1125
Vth + 75
VEE
150
VCC − 75
VCC
Vth − 75
2800
mV
mV
mV
mV
VIHD
Differential Input HIGH Voltage
VILD
Differential Input LOW Voltage
VCMR
Input Common Mode Range (Differential Configuration) (Note 8)
VID Differential Input Voltage Swing (VIHD − VILD)
IIH
Input HIGH Current
CLKx / CLKx
(VTx Open)
IIL
Input LOW Current
CLKx / CLKx
(VTx Open)
Single−Ended LVCMOS / LVTTL Control Inputs
1200
VEE
1125
150
10
−10
VCC
VCC − 150
VCC − 75
2800
40
10
mV
mV
mV
mV
mA
mA
VIH Single−ended Input HIGH Voltage
VIL Single−ended Input LOW Voltage
IIH Input HIGH Current
CLKSEL, DIVSEL, EN
MR
2000
VEE
40
−10
VCC
mV
800 mV
115 mA
10
IIL Input LOW Current
CLKSEL, DIVSEL, EN
MR
−10
−115
10 mA
−40
Termination Resistors
RTIN
Internal Input Termination Resistor (Measured across CLKx and CLKx)
80
100 120 W
RTIN
Internal Input Termination Resistor (Measured from CLKx to VTx)
40 50 60 W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. LVPECL outputs require 50 W receiver termination resistors to VCC − 2 V for proper operation.
5. Input and output parameters vary 1:1 with VCC.
6. Vth is applied to the complementary input when operating in single−ended mode.
7. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
8. VCMR min varies 1:1 with VEE, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input
signal.
http://onsemi.com
5
5 Page 
Driver
Device
Q
Q
NB4L339
ZO = 50 W
ZO = 50 W
50 W
D
Receiver
Device
D
50 W
VTT
VTT = VCC − 2.0 V
Figure 21. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices)
ORDERING INFORMATION
Device
Package
Shipping†
NB4L339MNG
QFN32
(Pb−free)
74 Units / Tray
NB4L339MNR4G
QFN32
(Pb−free)
1000 / Tape & Reel
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet NB4L339.PDF ] | |
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