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PDF AND8066 Data sheet ( Hoja de datos )
| Número de pieza | AND8066 | |
| Descripción | Interfacing | |
| Fabricantes | ON Semiconductor | |
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AND8066/D
Interfacing with ECLinPS
Prepared by: Paul Shockman
ON Semiconductor Logic Applications Engineering
STANDARD ECL INTERFACE: DIFFERENTIAL
DRIVER AND RECEIVER
A typical Emitter Coupled Logic (ECL) circuit interface
may be defined as a differential driver device sending a paired
set of commentary signals – True and Invert – over a pair of
standard, controlled impedance lines to an ECL differential
receiver device. A typical ECL output line driver consists of
a bipolar transistor in an Emitter Follower configuration with
the collector at VCC power supply rail and the emitter pinned
out. A standard, typical differential ECL receiver consists of
a pair of bipolar transistors in a differential configuration with
the True and Invert signals providing base drives to the two
base inputs. Proper differential levels are specified as Vpp and
VIHCMR. When an input is interconnected as a differential
signal, the DC Single Ended parameters of VIL and VIH do not
apply. Terminations are required to preserve optimum signal
integrity, as shown in Figure 1. The standard, controlled
impedance lines assume a sufficient return current capability.
VCC
Q
True
VCC
DQ
Q
VEE
Invert
DQ
VEE
VTT
Figure 1. Standard Differential ECL Interconnect
SINGLE–ENDED INTERFACE
Signals may be imported as full differential lines or as a
Single–Ended (SE) line interconnection. The SE
interconnection may be seen as a special variation of the
typical differential interface using only one driver source
trace line. This single trace line drives a (Base) input pin of
the receiver, as shown in Figure 2. Although a receiver may
present only a single, dedicate SE input pin instead of a
differential input pair of pins, such a receiver still would have
a differential structure with the unavailable input controlled
by internal circuitry.
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APPLICATION NOTE
VCC
True
VCC
VEE
VEE
VTT
Figure 2. Standard Single–Ended ECL Interconnect
Single–ended receiver input levels are specified in data
sheets DC CHARACTERISTICS block as VIH and VIL
Parameters. Each temperature has a minimum and
maximum limit pair to VIH and VIL parameters, thus
defining the Single–Ended input swing, Vpp(SE). The
Vpp(SE) ranges from 595 mV to 890 mV, depending on the
temperature and family. The Vpp(SE) limits constitute the
receiver device’s input single–ended sensitivity.
Both output lines of the typical differential output may
drive two independent single–ended receivers separately (see
Figure 3).
VCC
VCC
Q
Q
VEE
True
Invert
Q
VEE
VTT
VCC
Q
VTT VEE
Figure 3. Differential Driver with Independent
Standard Single–Ended Receivers
© Semiconductor Components Industries, LLC, 2002
May, 2002 – Rev. 2
1
Publication Order Number:
AND8066/D
1 page  
–0.8
–1.0
–1.2
85°C
–1.4
25°C
–30°
C
–1.6
–1.8
AND8066/D
–0.8
–1.0
–1.2
70°C
–1.4
–1.6
25°C
0°C
–1.8
–2.0
–1.8
–1.6 –1.4 –1.2
Vin, (RELATIVE TO VCC)
–1.0
–0.8
Figure 15. 10K Series Vin vs. Vout Transfer Curves
–2.0
–1.8
–1.6 –1.4 –1.2
Vin, (RELATIVE TO VCC)
–1.0
–0.8
Figure 16. 10KH Series Vin vs. Vout Transfer Curves
The difference in the DC behavior of the inputs and outputs
of the two different standards necessitates caution when
mixing the two technologies in single–ended designs. Output
levels become critical to the receiver when the VOH minimum,
VOHA, drives into the receiver as the VIH minimum. Levels are
also critical when the driver VOL maximum, VOLA, drives into
the receiver as the VIL maximum.
VOH(max)
VIH(max)
VOH(min)
VOHA
VOL(max)
VOLA
VIH(min)
VIL(max)
VOL(min)
VIH(min)
Figure 17. Single–Ended Noise Margin
Noise margin quantifies the susceptibility of a driver and
receiver interface to any non–signal voltage levels and
therefore risking false switching. Two measurements –
NOISE MARGIN HIGH and NOISE MARGIN LOW –
describe the false switching risk across temperature as
follows:
NOISE MARGIN(HIGH) = VOH(min) – VIH(min)
NOISE MARGIN(LOW) = VOL(max) – VIL(max)
An MC10EP16DT, operating in LVPECL mode with 3.3 V
on VCC and 0.0 V on VEE, interfaced to an MC10EP16DT
receiver, single–ended, has a noise margin at the specification
ambient temperature shown in Table 1. Notice the safety
margin levels are positive for NOISE MARGIN HIGH
indicating the driver exceeds the receiver’s requirement for a
minimum and the delta is positive. For a NOISE MARGIN
LOW, the driver must be below the receiver’s maximum and
the delta is negative.
Table 1. Noise Margins: MC10EP16DT Interfaced to
an MC10EP16DT Receiver
10 to 10 Noise
Margin HIGH
Temp.
VOH(min) –
VIH(min)
Delta
(mV)
–40°C
2165 – 2090
75
25°C
2230 – 2155
75
85°C
2290 – 2215
75
10 to 10 Noise
Margin LOW
Temp.
–40 °C
VOL(max) –
VIL(max)
1615 – 1690
Delta
(mV)
–40
25°C
1680 – 1755
–75
85°C
1740 – 1810
–70
When a 10 Series device drives a 100 Series device
single–ended, the noise margins become a risk factor requiring
careful evaluation as indicated in Table 2.
Table 2. Noise Margins: MC10EP16DT Interfaced to
an MC100EP16DT Receiver
10 to 100 Noise
Margin HIGH
Temp.
–40°C
25°C
85°C
VOH(min) – VIH(min)
2165 – 2075
2230 – 2075
2290 – 2075
Delta
(mV)
90
155
215
10 to 100 Noise
Margin LOW
Temp.
–40 °C
25°C
85°C
VOL(max) – VIL(max)
1615 – 1675
1680 – 1675
1740 – 1675
Delta
(mV)
–60
5
65
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