DataSheet26.com

HFCT-5903E PDF даташит

Спецификация HFCT-5903E изготовлена ​​​​«Hewlett-Packard» и имеет функцию, называемую «MT-RJ Duplex Single Mode Transceiver».

Детали детали

Номер произв HFCT-5903E
Описание MT-RJ Duplex Single Mode Transceiver
Производители Hewlett-Packard
логотип Hewlett-Packard логотип 

12 Pages
scroll

No Preview Available !

HFCT-5903E Даташит, Описание, Даташиты
www.DataSheet4U.com
Agilent HFCT-5903E MT-RJ Duplex
Single Mode Transceiver
Data Sheet
Description
The HFCT-5903E transceiver is a
high performance, cost effective
module for serial optical data
communications applications
specified for a signal rate of
125 MBd. It is designed to provide
an FDDI SMF-PMD1 link for FDDI
or Fast Ethernet applications and
is also compatible with ATM/
SONET/SDH transceivers. The
HFCT-5903 does not include a nose
shield and is not recommended
due to the potential degradation
of EMI performance in a complete
system. The HFCT-5903 is
available on the rare occasion that
a system mechanical design may
not allow for a nose shield.
It incorporates Agilent’s high
performance, reliable, long
wavelength optical devices and
proven circuit technology to give
long life and consistent service.
The transmitter section uses an
advanced SMQW Fabry Perot
laser with full IEC 825 and CDRH
Class I eye safety.
The receiver section uses a
MOVPE grown planar PIN
photodetector for low dark
current and excellent
responsivity.
A pseudo-ECL logic interface
simplifies interface to external
circuitry.
This module is designed for single
mode fiber and operates at a
nominal wavelength of 1300 nm.
Features
• MT-RJ duplex single mode
transceiver
• Power compliant to ANSI
X3.184- 1993 standard for FDDI
SMF-PMD category 1
optoelectronic performance
• Single +3.3 V power supply
• Multisourced 2 x 5 pin
configuration
• Interchangeable with LED
multisourced 2 x 5 transceivers
• Unconditionally eye safe
laser IEC 825/CDRH Class 1
compliant
• Temperature range:
0°C to +70°C
Applications
• FDDI SMF-PMD1
• Fast ethernet
• ATM compatible









No Preview Available !

HFCT-5903E Даташит, Описание, Даташиты
Connection Diagram
RX TX
Mounting Studs/
Solder Posts
Package
Grounding Tabs
Top
View
RECEIVER SIGNAL GROUND f 1 10 f
RECEIVER POWER SUPPLY f 2
9f
SIGNAL DETECT
f3
8f
RECEIVER DATA OUT BAR
f4
7f
RECEIVER DATA OUT
f5
6f
TRANSMITTER DATA IN BAR
TRANSMITTER DATA IN
TRANSMITTER DISABLE
TRANSMITTER SIGNAL GROUND
TRANSMITTER POWER SUPPLY
Pin Descriptions:
Pin 1 Receiver Signal Ground
VEE RX:1
Directly connect this pin to the
receiver ground plane.
Pin 2 Receiver Power Supply
VCC RX:
Provide +3.3 V dc via the
recommended receiver power
supply filter circuit. Locate the
power supply filter circuit as
close as possible to the VCC RX
pin.
Pin 3 Signal Detect SD:
Normal optical input levels to the
receiver result in a logic “1”
output.
Low optical input levels to the
receiver result in a fault condition
indicated by a logic “0” output.
This Signal Detect output can be
used to drive a PECL input on an
upstream circuit, such as Signal
Detect input or Loss of Signal-bar.
Pin 4 Receiver Data Out Bar RD-:
No internal terminations are
provided. See recommended
circuit schematic.
Pin 5 Receiver Data Out RD+:
No internal terminations are
provided. See recommended
circuit schematic.
Pin 6 Transmitter Power Supply
VCC TX:
Provide +3.3 V dc via the
recommended transmitter power
supply filter circuit. Locate the
power supply filter circuit as
close as possible to the VCC TX
pin.
Pin 7 Transmitter Signal Ground
VEE TX:
Directly connect this pin to the
transmitter ground plane.
Pin 8 Transmitter Disable TDIS:
Optional feature for laser based
products only. For laser based
products connect this pin to
+3.3 V TTL logic high “1” to
disable module. To enable module
connect to TTL logic low “0”.
Pin 9 Transmitter Data In TD+:
No internal terminations are
provided. See recommended
circuit schematic.
Pin 10 Transmitter Data In Bar TD-:
No internal terminations are
provided. See recommended
circuit schematic.
Mounting Studs/Solder Posts
The two mounting studs are
provided for transceiver
mechanical attachment to the
circuit board. It is recommended
that the holes in the circuit board
be connected to chassis ground.
Package Grounding Tabs
Connect four package grounding
tabs to signal ground.
Note: 1. The Transmitter and Receiver VEE connections are commoned within the module.
2









No Preview Available !

HFCT-5903E Даташит, Описание, Даташиты
Functional Description
Receiver Section
Design
The receiver section contains an
InGaAs/InP photo detector and a
preamplifier mounted in an
optical subassembly. This optical
subassembly is coupled to a
postamp/decision circuit on a
separate circuit board.
The postamplifier is ac coupled to
the preamplifier as illustrated in
Figure 1. The coupling capacitor
is large enough to pass the FDDI
test pattern at 125 MBd and the
SONET/SDH test pattern at
155 MBd without significant
distortion or performance penalty
If a lower signal rate, or a code
which has significantly more low
frequency content is used,
sensitivity, jitter and pulse
distortion could be degraded.
Figure 1 also shows a filter
network which limits the
bandwidth of the preamp output
signal. The filter is designed to
bandlimit the preamp output
noise and thus improve the
receiver sensitivity.
These components will also
reduce the sensitivity of the
receiver as the signal bit rate is
increased above 155 MBd.
Noise Immunity
The receiver includes internal
circuit components to filter
power supply noise. Under some
conditions of EMI and power
supply noise, external power
supply filtering may be necessary.
If receiver sensitivity is found to
be degraded by power supply
noise, the filter network
illustrated in Figure 3 may be
used to improve performance.
The values of the filter
components are general
recommendations and may be
changed to suit a particular
system environment. Shielded
inductors are recommended.
Terminating the Outputs
The PECL Data outputs of the
receiver may be terminated with
the standard Thevenin-equivalent
50 ohm to VCC - 2 V termination.
Other standard PECL terminating
techniques may be used.
The two outputs of the receiver
should be terminated with
identical load circuits to avoid
unnecessarily large ac current in
VCC. If the outputs are loaded
identically the ac current is
largely nulled. The SD output of
the receiver is PECL logic and
must be loaded if it is to be used.
The signal detect circuit is much
slower that the data path, so the
ac noise generated by an
asymmetrical load is negligible.
Power consumption may be
reduced by using a higher than
normal load impedance for the SD
output. Transmission line effects
are not generally a problem as the
switching rate is slow.
The Signal Detect Circuit
The signal detect circuit works by
sensing the peak level of the
received signal and comparing
this level to a reference.
TRANS-
IMPEDANCE
PRE-
AMPLIFIER
FILTER
AMPLIFIER
PECL
OUTPUT
BUFFER
DATA OUT
DATA OUT
GND
Figure 1. Receiver Block Diagram
SIGNAL
DETECT
CIRCUIT
PECL
OUTPUT
BUFFER
SD
3










Скачать PDF:

[ HFCT-5903E.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
HFCT-5903EMT-RJ Duplex Single Mode TransceiverHewlett-Packard
Hewlett-Packard

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск