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PDF NCV7380 Data sheet ( Hoja de datos )
| Número de pieza | NCV7380 | |
| Descripción | LIN Transceiver | |
| Fabricantes | ON Semiconductor | |
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NCV7380
Advance Information
LIN Transceiver
The NCV7380 is a physical layer device for a single wire data link
capable of operating in applications where high data rate is not
required and a lower data rate can achieve cost reductions in both the
physical media components and in the microprocessor which uses
the network. The NCV7380 is designed to work in systems
developed for LIN 1.3 or LIN 2.0. The IC furthermore can be used in
ISO9141 systems.
Because of the very low current consumption of the NCV7380 in
recessive state, it’s suitable for ECU applications with low standby
current requirements, whereby no sleep/wake−up control from the
microprocessor is necessary.
Features
• Operating Voltage VS = 6.0 to 18 V
• Low Current Consumption of Typ. 24 mA
• LIN−Bus Transceiver:
♦ Slew Rate Control for Good EMC Behavior
♦ Fully Integrated Receiver Filter
♦ BUS Input Voltage −27 V to 40 V
♦ Integrated Termination Resistor for LIN Slave Nodes (30 kW)
♦ Baud Rate up to 20 kBaud
♦ Will Work in Systems Designed for either LIN 1.3 or LIN 2.0
• Compatible to ISO9141 Functions
• High EMI Immunity
• Bus Terminals Protect Against Short−Circuits and Transients in the
Automotive Environment
• Bus Pin High Impedance During Loss of Ground and Undervoltage
Conditions
• Thermal Overload Protection
• High Signal Symmetry for use in RC–Based Slave Nodes up to 2%
Clock Tolerance when Compared to the Master Node
• "4.0 kV ESD Protection on all Pins
• NCV Prefix for Automotive and Other Applications Requiring Site
and Change Control
http://onsemi.com
8
1
SO−8
D SUFFIX
CASE 751
MARKING
DIAGRAM
8
V7380
ALYW
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
PIN CONNECTIONS
RxD 1
NC 2
VCC 3
TxD 4
8 NC
7 VS
6 BUS
5 GND
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCV7380D
SO−8
95 Units/Rail
NCV7380DR2
SO−8 2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
© Semiconductor Components Industries, LLC, 2004
May, 2004 − Rev. P3
1
Publication Order Number:
NCV7380/D
1 page  
NCV7380
ELECTRICAL CHARACTERISTICS (continued) (VS = 6.0 to 18 V, VCC = 4.5 to 5.5 V and TA = −40 to 125°C unless otherwise noted.)
Characteristic
Symbol
Condition
Min Typ Max Unit
TXD
High Level Input Voltage
Low Level Input Voltage
TxD Pull Up Resistor
RXD
Low Level Output Voltage
Leakage Current
AC CHARACTERISTICS
Vih
Vil
RIH_TXD
Rising Edge
Falling Edge
VTxD = 0 V
Vol_rxd
Vleak_rxd
IRxD = 2.0 mA
VRxD = 5.5 V, Recessive
−
−
0.7*VCC
V
0.3*VCC
−
−V
10 15 20 kW
−
−1.0
−
−
0.9 V
1.0 mA
Propagation Delay Transmitter
(Notes 9 and 11)
Propagation Delay Transmitter Symmetry
(Notes 7 and 11)
ttrans_pdf
ttrans_pdr
ttrans_sym
Bus Loads: 1.0 KW/1.0 nF,
660 W/6.8 nF, 500 W/10 nF
Calculate ttrans_pdf − ttrans_pdr
−
−2.0
−
−
5.0 ms
2.0 ms
Propagation Delay Receiver
(Notes 7, 8, 9, 11 and 14)
Propagation Delay Receiver Symmetry
(Notes 7 and 8)
trec_pdf
trec_pdr
trec_sym
CRxD = 20 pF
Calculate ttrans_pdf − ttrans_pdr
−
−1.5
−
−
6.0 ms
1.5 ms
Slew Rate Rising and Falling Edge,
High Battery (Notes 7 and 12)
tSR_HB
Bus Loads: VS = 18 V,
1.0 2.0 3.0 V/ms
1.0 KW/1.0 nF, 660 W/6.8 nF,
500 W/10 nF
Slew Rate Rising and Falling Edge,
Low Battery (Notes 7 and 12)
tSR_LB
Bus Loads: VS = 7.0 V,
0.5 2.0 3.0 V/ms
1.0 KW/1.0 nF, 660 W/6.8 nF,
500 W/10 nF
Slope Symmetry, High Battery
(Notes 7 and 12)
Bus Duty Cycle (Notes 8 and 15)
Receiver Debounce Time
(Notes 10, 13 and 14)
tssym_HB
Bus Loads: VS = 18 V,
1.0 KW/1.0 nF, 660 W/6.8 nF,
500 W/10 nF, Calculate
tsdom−tsrec
−5.0
−
5.0 ms
D1
Calculate tBUS_rec(min)/100 ms
0.396
−
− ms/ms
D2
Calculate tBUS_rec(max)/100 ms
−
− 0.581 ms/ms
trec_deb
BUS Rising and Falling Edge
1.5
−
4.0 ms
7. In accordance to LIN physical layer specification 1.3.
8. In accordance to LIN physical layer specification 2.0.
9. Propagation delays are not relevant for LIN protocol transmission, only symmetry.
10. No production test, guaranteed by design and qualification.
11. See Figure 2 − Input/Output Timing.
12. See Figure 7 − Slope Time Calculation.
13. See Figure 3 − Receiver Debouncing.
14. This parameter is tested by applying a square wave to the bus. The minimum slew rate for the bus rising and falling edges is 50 V/ms.
15. See Figure 8 − Duty Cycle Measurement and Calculation.
http://onsemi.com
5
5 Page 
NCV7380
tBit tBit
TxD
100%
VSUP
BUS
58.1%
28.4%
0%
GND
tdom(max)
tdom(min)
trec(min)
74.4%
42.2%
58.1%
trec(max)
28.4%
RxD
Figure 8. Duty Cycle Measurement and Calculation in Accordance to LIN Physical Layer Specification 2.0
Duty Cycle Calculation
With the timing parameters shown in Figure 8 two duty
cycles, based on trec(min) and trec(max) can be calculated as
follows:
D1* = trec(min)/(2 x tBit)
D2* = trec(max)/(2 x tBit)
For proper operation at 20 KBit/s (bit time is 50 ms) the
LIN driver has to fulfill the duty cycles specified in the AC
characteristics for supply voltages of 7...18 V and the three
defined standard loads.
Due to this simple definition there is no need to measure
slew rates, slope times, transmitter delays and dominant
voltage levels as specified in the LIN physical layer
specification 1.3.
The devices within the D1/D2 duty cycle range also
operates in applications with reduced bus speed of
10.4 KBit/s or below.
In order to minimize EME, the slew rates of the
transmitter can be reduced (by up to [ 2 times). Such
devices have to fulfill the duty cycle definition D3/D4 in
the LIN physical layer specification 2.0. Devices within
this duty cycle range cannot operate in higher frequency
20 KBit/s applications.
*D1 and D2 are defined in the LIN protocol specification 2.0.
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11
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| PDF Descargar | [ Datasheet NCV7380.PDF ] | |
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