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PDF CAT9554 Data sheet ( Hoja de datos )
| Número de pieza | CAT9554 | |
| Descripción | 8-Bit I2C and SMBus I/O Port | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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CAT9554, CAT9554A
8-bit I2C and SMBus I/O Port with Interrupt
FEATURES
I 400kHz I2C bus compatible*
I 2.3V to 5.5V operation
I Low stand-by current
I 5V tolerant I/Os
I 8 I/O pins that default to inputs at power-up
I High drive capability
I Individual I/O configuration
I Polarity inversion register
I Active low interrupt output
I Internal power-on reset
I No glitch on power-up
I Noise filter on SDA/SCL inputs
I Cascadable up to 8 devices
I Industrial temperature range
I RoHS-compliant 16-lead SOIC and TSSOP, and
16-pad TQFN (4 x 4 mm) packages
APPLICATIONS
I White goods (dishwashers, washing machines)
I Handheld devices (cell phones, PDAs, digital
cameras)
I Data Communications (routers, hubs and
servers)
DESCRIPTION
The CAT9554 and CAT9554A are CMOS devices that
provide 8-bit parallel input/output port expansion for I2C
and SMBus compatible applications. These I/O
expanders provide a simple solution in applications
where additional I/Os are needed: sensors, power
switches, LEDs, pushbuttons, and fans.
The CAT9554/9554A consist of an input port register, an
output port register, a configuration register, a polarity
inversion register and an I2C/SMBus-compatible serial
interface.
Any of the eight I/Os can be configured as an input or
output by writing to the configuration register. The system
master can invert the CAT9554/9554A input data by
writing to the active-high polarity inversion register.
The CAT9554/9554A features an active low interrupt
output which indicates to the system master that an input
state has changed.
The device’s extended addressing capability allows up
to 8 devices to share the same bus. The CAT9554A is
identical to the CAT9554 except the fixed part of the I2C
slave address is different. This allows up to 16 of devices
(eight CAT9554 and eight CAT9554A) to be connected
on the same bus.
For Ordering Information details, see page 15.
BLOCK DIAGRAM
A0
A1
A2
SCL
SDA
INPUT
FILTER
I2C/SMBUS
CONTROL
8-BIT
WRITE pulse
READ pulse
INPUT/
OUTPUT
PORTS
VCC
VSS
POWER-ON
RESET
NOTE: ALL I/Os ARE SET TO INPUTS AT RESET
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
LP
FILTER
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7 VCC
INT
Doc. No. 25088, Rev. B
1 page  
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AC TEST CONDITIONS
Input Rise and Fall time
CMOS Input Voltages
CMOS Input Reference Voltages
TTL Input Voltages
TTL Input Reference Voltages
Output Reference Voltages
Output Load: SDA, INT
Output Load: I/Os
CAT9554, CAT9554A
< = 10ns
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
0.4V to 2.4V
0.8V, 2.0V
0.5VCC
Current Souce IOL = 3mA; CL = 100pF
Current Source: IOL/IOH = 10mA; CL = 50pF
tF tHIGH tR
tLOW
tLOW
SCL
tSU:STA
tHD:DAT
tHD:STA
tSU:DAT
SDA IN
SDA OUT
tAA tDH
Figure 1. 2-Wire Serial Interface Timing
tSU:STO
tBUF
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 25088, Rev. B
5 Page 
www.DataSheet4U.com
CAT9554, CAT9554A
Power-On Reset Operation
When the power supply is applied to VCC pin, an internal
power-on reset pulse holds the CAT9554/9554A in a
reset state until VCC reaches VPOR level. At this point, the
reset condition is released and the internal state ma-
chine and the CAT9554/9554A registers are initialized
to their default state.
slave address
R/W
S 0 1 0 0 A2 A1 A0 0 A
acknowledge from slave
slave address
R/W
COMMAND BYTE
A S 0 1 0 0 A2 A1 A0 1 A
acknowledge from slave
acknowledge from slave
acknowledge
from master
data from register
DATA
first byte
A
At this moment master-transmitter becomes
master-receiver and slave-receiver
becomes slave-transmitter
Figure 11. Read from Register
no acknowledge
from master
data from register
DATA
last byte
NA P
SCL
12 34 56 78 9
slave address
R/W
SDA S 0 1 0 0 A2 A1 A0 1 A
start condition
acknowledge
from slave
READ FROM
PORT
DATA INTO
PORT
DATA 1
tPH
data from port
DATA 1
A
acknowledge from master
DATA 2
DATA 3
tPS
data from port
DATA 4
NA P
no acknowledge from master
stop
condition
DATA 4
INT
tIV
tIR
Figure 12. Read Input Port Register
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 25088, Rev. B
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet CAT9554.PDF ] | |
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