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PDF HDMP-1637A Data sheet ( Hoja de datos )
| Número de pieza | HDMP-1637A | |
| Descripción | Gigabit Ethernet SerDes Circuit | |
| Fabricantes | Hewlett-Packard | |
| Logotipo |  |
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Gigabit Ethernet SerDes Circuit
with Differential PECL Clock
Inputs
HDMP-1637A SerDes
Features
• IEEE 802.3z Gigabit
Ethernet Compatible,
Supports 1250 MBd Gigabit
Ethernet
• Based on X3T11 “10 Bit
Specification”
• Low Power Consumption
• 10 mm 64-pin PQFP Package
• Transmitter and Receiver
Functions Incorporated
onto a Single IC
• 5-Volt Tolerant I/Os
• 10 Bit Wide Parallel TTL
Compatible I/Os
• Single +3.3 V Power Supply
• Differential PECL Clock
Inputs
• 2 kV Human Body ESD
Protection on all Pins
Applications
• 1250 MBd Gigabit
Ethernet Interface
• High Speed Proprietary
Interface
• Backplane Serialization /
Bus Extender
Description
The HDMP-1637A transceiver is a
single silicon bipolar integrated
circuit packaged in a plastic QFP
package. It provides a low-cost,
low-power physical layer solution
for 1250 MBd Gigabit Ethernet or
proprietary link interfaces. It
provides complete Serialize/
Deserialize (SerDes) for copper
transmission, incorporating both
the Gigabit Ethernet transmit and
receive functions into a single
device.
This chip is used to build a high
speed interface (as shown in
Figure 1) while minimizing board
space, power, and cost. It is
compatible with the IEEE 802.3z
specification.
The transmitter section accepts
10-bit wide parallel TTL data and
serializes this data into a high
speed serial data stream. The
parallel data is expected to be
“8B/10B” encoded data, or
equivalent. This parallel data is
latched into the input register of
the transmitter section on the
rising edge of the 125 MHz
reference clock (used as the
transmit byte clock).
The transmitter section’s PLL
locks to this user supplied 125
MHz byte clock. This clock is then
multiplied by 10, to generate the
1250 MHz serial signal clock used
to generate the high speed output.
The high speed outputs are
capable of interfacing directly to
copper cables for electrical
transmission or to a separate fiber
optic module for optical
transmission.
The receiver section accepts a
serial electrical data stream at
1250 MBd and recovers the
original 10-bit wide parallel data.
The receiver PLL locks onto the
incoming serial signal and
recovers the high speed serial
clock and data. The serial data is
converted back into 10-bit parallel
data, recognizing the 8B/10B
comma character to establish byte
alignment.
The recovered parallel data is
presented to the user at TTL
compatible outputs. The receiver
section also recovers two 62.5
MHz receiver byte clocks which
are 180 degrees out of phase with
each other. The parallel data is
properly aligned with the rising
edge of alternating clocks.
For test purposes, the transceiver
provides for on-chip local loop-
back functionality controlled
through an external input pin.
Additionally, the byte
synchronization feature may be
disabled. This may be useful in
proprietary applications which use
alternative methods to align the
parallel data.
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in handling
and assembly of this component to prevent damage and/or degradation which may be induced by
electrostatic discharge (ESD).
1 page  
5
HDMP-1637A (Transmitter Section)
Timing Characteristics
TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V
Symbol
Parameter
tsetup
Setup Time
thold
t_txlat[1]
Hold Time
Transmitter Latency
Units
nsec
nsec
nsec
bits
Min.
1.5
1.0
Typ.
3.5
4.4
Max.
Note:
1. The transmitter latency, as shown in Figure 4, is defined as the time between the latching in of the parallel data word (as triggered
by the rising edge of the transmit byte clock, REFCLK) and the transmission of the first serial bit of that parallel word (defined by
the rising edge of the first bit transmitted).
REFCLK
tSETUP
TX[9]-TX[0]
DATA
DATA
DATA
Figure 3. Transmitter Section Timing.
tHOLD
DATA
DATA
0.0 V AC
2.0 V
0.8 V
DATA BYTE A
DATA BYTE B
± DOUT T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T0 T1 T2 T3 T4 T5
t_TXLAT
TX[0]-TX[9]
DATA BYTE B
DATA BYTE C
REFCLK
0.0 V AC
Figure 4. Transmitter Latency.
5 Page 
11
*GND
TX[0]
TX[1]
TX[2]
*VCC
TX[3]
TX[4]
TX[5]
TX[6]
*VCC
TX[7]
TX[8]
TX[9]
*GND
GND_TXA
TXCAP1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5 44
6 43
7
8
HDMP-1637A
42
41
9
xxxx-x Rz.zz
40
10 39
11 S YYWW 38
12 37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RXCAP0
BYTSYNC
GND_RXTTL
RX[0]
RX[1]
RX[2]
VCC_RXTTL
RX[3]
RX[4]
RX[5]
RX[6]
VCC_RXTTL
RX[7]
RX[8]
RX[9]
GND_RXTTL
xxxx-x = WAFER LOT NUMBER–BUILD NUMBER
Rz.zz = DIE REVISION
S = SUPPLIER CODE
YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK)
COUNTRY = COUNTRY OF MANUFACTURE
(MARKED ON BACK OF DEVICE)
*N/C: THIS PIN IS CONNECTED TO AN ISOLATED PAD AND HAS NO FUNCTIONALITY.
IT CAN BE LEFT OPEN, HOWEVER, TTL LEVELS CAN ALSO BE APPLIED TO THIS PIN.
*VCC: THIS PIN IS BONDED TO AN ISOLATED PAD AND HAS NO FUNCTIONALITY.
HOWEVER, IT IS RECOMMENDED THAT THIS PIN BE CONNECTED TO VCC IN ORDER
TO CONFORM WITH THE X3T11 "10-BIT SPECIFICATION," AND TO HELP DISSIPATE HEAT.
*GND: THIS PIN IS BONDED TO AN ISOLATED PAD AND HAS NO FUNCTIONALITY.
HOWEVER, IT IS RECOMMENDED THAT THIS PIN BE CONNECTED TO GND IN ORDER TO
CONFORM WITH THE X3T11 "10-BIT SPECIFICATION," AND TO HELP DISSIPATE HEAT.
HDMP-1637 fig 11
Figure 11. HDMP-1637A (TRx) Package Layout and Marking, Top View.
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet HDMP-1637A.PDF ] | |
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