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PDF NTMSD3P303R2 Data sheet ( Hoja de datos )
| Número de pieza | NTMSD3P303R2 | |
| Descripción | P-Channel Enhancement-Mode Power MOSFET and Schottky Diode Dual SO-8 Package | |
| Fabricantes | ON Semiconductor | |
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NTMSD3P303R2
FETKY™
P−Channel Enhancement−Mode
Power MOSFET and Schottky Diode
Dual SO−8 Package
Features
• High Efficiency Components in a Single SO−8 Package
• High Density Power MOSFET with Low RDS(on),
Schottky Diode with Low VF
• Independent Pin−Outs for MOSFET and Schottky Die
Allowing for Flexibility in Application Use
• Less Component Placement for Board Space Savings
• SO−8 Surface Mount Package,
Mounting Information for SO−8 Package Provided
Applications
• DC−DC Converters
• Low Voltage Motor Control
• Power Management in Portable and Battery−Powered Products, i.e.:
Computers, Printers, PCMCIA Cards, Cellular and Cordless Telephones
MOSFET MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Thermal Resistance −
Junction−to−Ambient (Note 1.)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 4.)
Thermal Resistance −
Junction−to−Ambient (Note 2.)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 4.)
Thermal Resistance −
Junction−to−Ambient (Note 3.)
Total Power Dissipation @ TA = 25°C
Continuous Drain Current @ TA = 25°C
Continuous Drain Current @ TA = 70°C
Pulsed Drain Current (Note 4.)
Operating and Storage
Temperature Range
VDSS
VGS
RθJA
PD
ID
ID
IDM
RθJA
PD
ID
ID
IDM
RθJA
PD
ID
ID
IDM
TJ, Tstg
−30
"20
V
V
171
0.73
−2.34
−1.87
−8.0
°C/W
W
A
A
A
100
1.25
−3.05
−2.44
−12
°C/W
W
A
A
A
62.5
2.0
−3.86
−3.10
−15
−55 to
+150
°C/W
W
A
A
A
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C (VDD =
−30 Vdc, VGS = −4.5 Vdc, Peak IL =
−7.5 Apk, L = 5 mH, RG = 25 Ω)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
EAS
TL
140 mJ
260 °C
1. Minimum FR−4 or G−10 PCB, Steady State.
2. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided),
Steady State.
3. Mounted onto a 2″ square FR−4 Board (1″ sq. 2 oz Cu 0.06″ thick single sided),
t ≤ 10 seconds.
4. Pulse Test: Pulse Width = 300 ms, Duty Cycle = 2%.
http://onsemi.com
MOSFET
−3.05 AMPERES
−30 VOLTS
0.085 W @ VGS = −10 V
SCHOTTKY DIODE
3.0 AMPERES
30 VOLTS
420 mV @ IF = 3.0 A
8
1
SO−8
CASE 751
STYLE 18
A 18 C
A
27
C
S 3 6D
GD
45
(TOP VIEW)
MARKING DIAGRAM
& PIN ASSIGNMENTS
Anode
Anode
Source
Gate
1 8 Cathode
27
3
E3P303
LYWW
Cathode
6
Drain
45
Drain
(Top View)
E3P303 = Device Code
L = Assembly Location
Y = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping†
NTMSD3P303R2 SO−8 2500/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2003
December, 2003 − Rev. 1
1
Publication Order Number:
NTMSD3P303R2/D
1 page  
NTMSD3P303R2
10000
VGS = 0 V
1000
TJ = 150°C
1200
1000
VDS = 0 V
Ciss
800
VGS = 0 V
TJ = 125°C
100
10
6 10 14 18 22 26 30
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Drain−to−Source Leakage Current
vs. Voltage
600 Crss
Ciss
400
Coss
200
TJ = 25°C
Crss
0
10 5
−VGS
0
5 10 15 20 25
−VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE
VOLTAGE (VOLTS)
Figure 8. Capacitance Variation
30
12
10
VDS
8
6
4 Q1
2
0
02
Q2
46
30 1000
VDS = −24 V
QT
25
ID = −3.05 A
VGS = −10 V
20 100
VGS
15
10 10
5
ID = −3.05 A
TJ = 25°C
0
8 10 12 14 16
1
1
td(off)
tf
td(on)
tr
10
100
Qg, TOTAL GATE CHARGE (nC)
RG, GATE RESISTANCE (Ω)
Figure 9. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
Figure 10. Resistive Switching Time Variation
vs. Gate Resistance
1000
VDS = −24 V
ID = −1.5 A
VGS = −4.5 V
3
VGS = 0 V
TJ = 25°C
2.5
2
100
tr
td(off)
1.5
tf 1
td(on)
0.5
10
1 10 100
RG, GATE RESISTANCE (Ω)
Figure 11. Resistive Switching Time Variation
vs. Gate Resistance
0
0.2 0.4 0.6 0.8 1 1.2
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 12. Diode Forward Voltage vs. Current
http://onsemi.com
5
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