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WED2ZL64512S PDF даташит

Спецификация WED2ZL64512S изготовлена ​​​​«White Electronic» и имеет функцию, называемую «Synchronous Pipeline NBL SRAM».

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Номер произв WED2ZL64512S
Описание Synchronous Pipeline NBL SRAM
Производители White Electronic
логотип White Electronic логотип 

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WED2ZL64512S Даташит, Описание, Даташиты
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White Electronic Designs
WED2ZL64512S
512K x 64 Synchronous Pipeline NBL SRAM
FEATURES
Fast clock speed: 166, 150, 133, and 100MHz
Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and
5.0ns
Seperate +2.5V ± 5% power supplys for core I/O
(VCC + VCCQ)
Double Word Write Control
Clock-controlled and registered addresses, data I/Os
and control signals
Packaging:
• 119 bump BGA package
Low capacitive bus loading
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process. WEDC’s 32Mb Sync
SRAM integrate two 512K x 32 SRAMs into a single
BGA package to provide 512K x 64 configuration. All
synchronous inputs pass through registers controlled by
a positive-edge-triggered single-clock input (CK). The
NBL or No Bus Latency Memory utilizes all the bandwidth
in any combination of operating cycles. Address, data
inputs, and all control signals except output enable are
synchronized to input clock. Output Enable controls the
outputs at any given time and to Asynchronous Input.
Write cycles are internally self-timed and initiated by the
rising edge of the clock input. This feature eliminates
complex off-chip write pulse generation and provides
increased timing flexibility for incoming signals.
NOTE: NBL = No Bus Latency is equivalent to the industry ZBT™ devices.
FIG. 1 PIN CONFIGURATION
(TOP VIEW)
123456789
A DQF DQF DQF DQF NC DQG DQG DQG DQG
B DQF DQF DQF DQF NC DQG DQG DQG DQG
C DQE DQE DQE DQE NC DQH DQH DQH DQH
D DQE DQE DQE DQE NC DQH DQH DQH DQH
E NC NC NC VCCQ VCCQ VCCQ NC NC NC
F SA VCCQ VCC VCC VCC VCC VCC VCCQ SA
G SA CE# VSS VSS VSS VSS VSS SA SA
H SA NC VSS WE1# VSS VSS VSS SA SA
J SA18 CE2# SSCK OE# NC NC NC SA1 SA0
K SA CE2 VSS WE0# VSS VSS VSS SA SA
L SA NC VSS VSS VSS VSS VSS SA SA
M SA VCCQ VCC VCC VCC VCC VCC VCCQ SA
N NC NC NC VCCQ VCCQ VCCQ NC NC NC
P DQD DQD DQD DQD NC DQA DQA DQA DQA
R DQD DQD DQD DQD NC DQA DQA DQA DQA
T DQC DQC DQC DQC NC DQB DQB DQB DQB
U DQC DQC DQC DQC NC DQB DQB DQB DQB
OEB
WEB_LW
CK
CS2B
CS2
CS1B
BLOCK DIAGRAM
SA 0 18
DQ 0 31
DQ 32 63
A0 – A18
OE#
WE#
CK
CS2#
CS2
CS1#
U1
DQ 0 31
512K x 36
WEB_HW
A0 – A18
OE#
WE#
CK
CS2#
CS2
CS1#
U2
DQ 0 31
512K x 36
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October 2001
Rev. 0
1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com









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WED2ZL64512S Даташит, Описание, Даташиты
White Electronic Designs
WED2ZL64512S
FUNCTION DESCRIPTION
The WED2ZL64512S is an NBL SSRAM designed to
sustain 100% bus bandwidth by eliminating turnaround
cycle when there is transition from Read to Write, or
vice versa. All inputs (with the exception of OE#) are
synchronized to rising clock edges.
Output Enable (OE#) can be used to disable the output
at any given time. Read operation is initiated when at
the rising edge of the clock, the address presented to
the address inputs are latched in the address register,
CKE# is driven low, the write enable input signals WE#
are driven high. The internal array is read between the first
rising edge and the second rising edge of the clock and
the data is latched in the output register. At the second
clock edge the data is driven out of the SRAM. During
read operation OE# must be driven low for the device to
drive out the requested data.
Write operation occurs when WE# is driven low at the
rising edge of the clock. The pipe-lined NBL SSRAM uses
a late-late write cycle to utilize 100% of the bandwidth. At
the first rising edge of the clock, WE# and address are
registered, and the data associated with that address is
required two cycle later.
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CEx#
H
L
L
X
L
L
NOTES:
WE# OE#
XX
CK
Address Accessed
N/A
Operation
Deselect
H L
Current Address
Read Cycle
H H
N/A
NOP/Dummy Read
X H
N/A
Dummy Read
L X
Current Address
Write Cycle
L X
N/A
NOP/Write Abort
1. X means “Don’t Care.”
2. The rising edge of clock is symbolized by ()
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WRITE# = L means Write operation in WRITE TRUTH TABLE.
WRITE# = H means Read operation in WRITE TRUTH TABLE.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October 2001
Rev. 0
2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com









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WED2ZL64512S Даташит, Описание, Даташиты
White Electronic Designs
WED2ZL64512S
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to Vss
-0.3V TA +3.6V
VIN (DQx)
-0.3V TA +3.6V
VIN (Inputs)
-0.3V TA +3.6V
Storage Temperature (BGA)
-55°C TA +125°C
Short Circuit Output Current
100mA
*Stress greater than those listed under “Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS (0°C TA 70°C)
Description
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Symbol
VIH
VIL
ILI
ILO
VOH
VOL
VCC
Conditions
0V VIN VCC
Output(s) Disabled, 0V VIN VCC
IOH = -1.0mA
IOL = 1.0mA
Min
1.7
-0.3
-5
-5
2.0
---
2.375
Max
VCC +0.3
0.7
5
5
---
0.4
2.625
NOTES: 1. All voltages referenced to VSS (GND)
Units
V
V
mA
mA
V
V
V
Notes
1
1
1
1
1
DC CHARACTERISTICS
Description
Power Supply
Current: Operating
Power Supply
Current: Standby
Clock Running
Standby Current
Symbol
ICC
ISB2
ISB4
Conditions
Device Selected; All Inputs VIL or VIH; Cycle
Time = TCYC MIN; VCC = MAX; Output Open
Device Deselected; VCC = MAX; All Inputs VSS + 0.2
or VCC - 0.2; All Inputs Static; CK Frequency = 0
Device Deselected; VCC = MAX; All Inputs
VSS + 0.2 or VCC - 0.2; Cycle Time = TCYC MIN
166 150 133 100
Typ MHZ MHZ MHZ MHZ
650 600 560 500
30 60 60 60 60
140 120 100 80
NOTES:
1. ICC is specified with no output current and increases with faster cycle times. ICC increases with faster cycle times and greater output loading.
2. Typical values are measured at 2.5V, 25°C, and 10ns cycle time.
Units Notes
mA 1, 2
mA 2
mA 2
Description
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
NOTES: 1. This parameter is sampled.
BGA CAPACITANCE
Symbol
CL
CO
CA
CCK
Conditions
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
TA = 25°C; f = 1MHz
Typ Max Units Notes
5 7 pF 1
6 8 pF 1
5 7 pF 1
3 5 pF 1
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
October 2001
Rev. 0
3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com










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WED2ZL64512SSynchronous Pipeline NBL SRAMWhite Electronic
White Electronic

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