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W982508AH PDF даташит

Спецификация W982508AH изготовлена ​​​​«Winbond» и имеет функцию, называемую «8M X 4 BANKS X 8 BIT SDRAM».

Детали детали

Номер произв W982508AH
Описание 8M X 4 BANKS X 8 BIT SDRAM
Производители Winbond
логотип Winbond логотип 

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W982508AH Даташит, Описание, Даташиты
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W982508AH
GENERAL DESCRIPTION
8M × 4 BANKS × 8 BIT SDRAM
W982508AH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
8M words × 4 banks × 8 bits. Using pipelined architecture and 0.175 µm process technology,
W982508AH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the
personal computer industrial standard, W982508AH is sorted into three speed grades: -7, -75 and -
8H. The -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the
PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W982508AH is ideal for main memory in
high performance applications.
FEATURES
3.3V ±0.3V Power Supply
Up to 143 MHz Clock Frequency
8,388,608 Words × 4 Banks × 8 Bits Organization
Auto Refresh and Self Refresh
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and Full Page
Burst Read, Single Writes Mode
Byte Data Controlled by DQM
Power-down Mode
Auto-precharge and Controlled Precharge
4K Refresh Cycles/64 mS
Interface: LVTTL
Packaged in TSOP II 54-pin, 400 mil - 0.80
KEY PARAMETERS
SYM.
DESCRIPTION
tCK Clock Cycle Time
tAC Access Time from CLK
tRP Precharge to Active Command
tRCD Active to Read/Write Command
ICC1 Operation Current (Single bank)
ICC4 Burst Operation Current
ICC6 Self-refresh Current
MIN.
/MAX.
Min.
Max.
Min.
Min.
Max.
Max.
Max.
-7
(PC133, CL2)
7 nS
5.4 nS
15 nS
15 nS
80 mA
100 mA
3 mA
-75
(PC133, CL3)
7.5 nS
5.4 nS
20 nS
20 nS
75 mA
95 mA
3 mA
-8H
(PC100)
8 nS
6 nS
20 nS
20 nS
70 mA
90 mA
3 mA
Publication Release Date: December 2000
- 1 - Revision A1









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W982508AH Даташит, Описание, Даташиты
PIN CONFIGURATION
VCC
DQ0
VCCQ
NC
DQ1
VSSQ
NC
DQ2
VCCQ
NC
DQ3
VSSQ
NC
VCC
NC
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
W982508AH
54 VSS
53 DQ7
52 VSSQ
51 NC
50 DQ6
49 VCCQ
48 NC
47 DQ5
46 VSSQ
45 NC
44 DQ4
43 VCCQ
42 NC
41 VSS
40 NC
39 DQM
38 CLK
37 CKE
36 A12
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 VSS
-2-









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W982508AH Даташит, Описание, Даташиты
W982508AH
PIN DESCRIPTION
PIN NO. PIN NAME FUNCTION
DESCRIPTION
2326, 22,
2936
20, 21
A0A12
BS0, BS1
Address
Bank Select
Multiplexed pins for row and column address.
Row address: A0A12. Column address: A0A9.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
2, 5, 8, 11, 44,
47, 50, 53
DQ0DQ7
Data Input/
Output
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
19 CS Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
18
RAS
Row Address
Strobe
the clock, RAS , CAS and WE define the
operation to be executed.
Column
17
CAS
Address Referred to RAS
Strobe
16 WE Write Enable Referred to RAS
The output buffer is placed at Hi-Z(with latency of 2)
39
DQM
Input/Output when DQM is sampled high in read cycle. In write
Mask
cycle, sampling DQM high will block the write
operation with zero latency.
38
CLK
Clock Inputs
System clock used to sample inputs on the rising edge
of clock.
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
4, 7, 10, 13,
15, 40, 42, 45,
48, 51
CKE
VCC
VSS
VCCQ
VSSQ
NC
CKE controls the clock activation and deactivation.
Clock Enable When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground Ground for input buffers and logic circuit inside DRAM.
Power (+3.3V) Separated power from VCC, to improve DQ noise
for I/O Buffer immunity.
Ground Separated ground from VSS, to improve DQ noise
for I/O Buffer immunity.
No Connection No connection
Publication Release Date: December 2000
- 3 - Revision A1










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