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PDF 74AUP2G38 Data sheet ( Hoja de datos )
| Número de pieza | 74AUP2G38 | |
| Descripción | Low Power Dual 2-Input NAND Gate | |
| Fabricantes | NXP Semiconductors | |
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74AUP2G38
Low-power dual 2-input NAND gate (open-drain)
Rev. 01 — 16 October 2006
Product data sheet
1. General description
The 74AUP2G38 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP2G38 provides the dual 2-input NAND gate with open-drain output. The output
of the device is an open drain and can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH wired-AND functions.
2. Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114-D Class 3A exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101-C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from −40 °C to +85 °C and −40 °C to +125 °C
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NXP Semiconductors
74AUP2G38
Low-power dual 2-input NAND gate (open-drain)
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Typ
Tamb = 25 °C
VIH HIGH-level input voltage
VCC = 0.8 V
VCC = 0.9 V to 1.95 V
0.70 × VCC -
0.65 × VCC -
VCC = 2.3 V to 2.7 V
VCC = 3.0 V to 3.6 V
1.6 -
2.0 -
VIL LOW-level input voltage VCC = 0.8 V
VCC = 0.9 V to 1.95 V
--
--
VCC = 2.3 V to 2.7 V
--
VCC = 3.0 V to 3.6 V
--
VOL LOW-level output voltage VI = VIH or VIL
IO = 20 µA; VCC = 0.8 V to 3.6 V
-
-
IO = 1.1 mA; VCC = 1.1 V
--
IO = 1.7 mA; VCC = 1.4 V
IO = 1.9 mA; VCC = 1.65 V
--
--
IO = 2.3 mA; VCC = 2.3 V
IO = 3.1 mA; VCC = 2.3 V
--
--
IO = 2.7 mA; VCC = 3.0 V
--
IO = 4.0 mA; VCC = 3.0 V
--
II
input leakage current
VI = GND to 3.6 V; VCC = 0 V to 3.6 V
-
-
IOZ OFF-state output current VI = VIH or VIL; VO = 0 V to 3.6 V;
VCC = 0 V to 3.6 V
-
-
IOFF
∆IOFF
power-off leakage current
additional power-off
leakage current
VI or VO = 0 V to 3.6 V; VCC = 0 V
VI or VO = 0 V to 3.6 V;
VCC = 0 V to 0.2 V
-
-
-
-
ICC
∆ICC
supply current
additional supply current
VI = GND or VCC; IO = 0 A;
VCC = 0.8 V to 3.6 V
VI = VCC − 0.6 V; IO = 0 A;
VCC = 3.3 V
--
--
CI input capacitance
VCC = 0 V to 3.6 V; VI = GND or VCC
-
0.7
CO output capacitance
VO = GND; VCC = 0 V
- 0.9
Max Unit
-V
-V
-V
-V
0.30 × VCC V
0.35 × VCC V
0.7 V
0.9 V
0.1
0.3 × VCC
0.31
0.31
0.31
0.44
0.31
0.44
±0.1
±0.1
V
V
V
V
V
V
V
V
µA
µA
±0.2 µA
±0.2 µA
0.5 µA
40 µA
- pF
- pF
74AUP2G38_1
Product data sheet
Rev. 01 — 16 October 2006
© NXP B.V. 2006. All rights reserved.
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13. Package outline
74AUP2G38
Low-power dual 2-input NAND gate (open-drain)
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
y
Z
8
5
pin 1 index
E
c
HE
A A2
A1
1
e
4
bp w M
detail X
A
X
vM A
Q
(A3)
θ
Lp
L
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1) E(2)
e
mm
1
0.15
0.00
0.85
0.60
0.12
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
HE
3.2
3.0
OUTLINE
VERSION
SOT765-1
IEC
REFERENCES
JEDEC
JEITA
MO-187
L Lp Q v w y Z(1) θ
0.4
0.40 0.21
0.15 0.19
0.2
0.13
0.1
0.4
0.1
8°
0°
EUROPEAN
PROJECTION
ISSUE DATE
02-06-07
Fig 9. Package outline SOT765-1 (VSSOP8)
74AUP2G38_1
Product data sheet
Rev. 01 — 16 October 2006
© NXP B.V. 2006. All rights reserved.
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| PDF Descargar | [ Datasheet 74AUP2G38.PDF ] | |
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