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W532 PDF даташит

Спецификация W532 изготовлена ​​​​«Cypress Semiconductor» и имеет функцию, называемую «Peak Reducing EMI Solution».

Детали детали

Номер произв W532
Описание Peak Reducing EMI Solution
Производители Cypress Semiconductor
логотип Cypress Semiconductor логотип 

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W532 Даташит, Описание, Даташиты
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W532
Features
Frequency Multiplying, Peak Reducing EMI Solution
Table 1. Output Frequency Range Selection
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the
output
• Selectable frequency range and multiplication factor
• Single 1.25% or 5% center spread output
• Integrated loop filter components
• Operates with a 3.3V or 5V supply
• Low power CMOS design
• Available in 16-pin SOIC
Key Specifications
Supply Voltages: ........................................VDD = 3.3V ±0.3V
or VDD = 5V ±10%
Frequency Range: .........................15 MHz Fout 120 MHz
Cycle to Cycle Jitter: ......................................... 150 ps (typ.)
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time ................................... 5 ns (max.)
OR2
0
0
1
1
OR1
0
1
0
1
Output Range
(Multiplication Factor Selection)
reserved
15 MHz FIN 30 MHz
30 MHz FIN 60 MHz
60 MHz FIN 120 MHz
Table 2. Modulation Width Selection
MW Output
0 Favg + 0.625% Fout Favg 0.625%
1 Favg + 2.5% Fout Favg 2.5%
Table 3. Input Frequency Range Selection
IR2 IR1
00
01
10
11
Input Range
reserved
15 MHz FIN 30 MHz
30 MHz FIN 60 MHz
60 MHz FIN 120 MHz
Simplified Block Diagram
3.3V or 5.0V
XTAL
Input
X1
X2
W532
Spread Spectrum
Output
(EMI suppressed)
3.3V or 5.0V
Pin Configuration
SOIC
X1
X2
AVDD
*OR1
NC
AGND
^OR2
*SSON#
1
2
3
4
5
6
7
8
16 VDD
15 GND
14 IR1^
13 IR2^
12 SSOUT
11 GND
10 VDD
9 MW*
Oscillator or
Reference Input
X1
W532
Spread Spectrum
Output
(EMI suppressed)
Notes:
1. ^ pins have internal pull-up
2. * pins have internal pull-down
PREMIS is a trademark of Cypress Semiconductor.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07253 Rev. *A
Revised December 28, 2002









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W532 Даташит, Описание, Даташиты
W532
Pin Definitions
Pin Name
SSOUT
CLKIN or X1
Pin No.
12
1
NC or X2
SSON#
2
8
MW 9
IR1:2
14, 13
OR1:2
VDD
GND
NC
4, 7
3, 10, 16
6, 11, 15
5
Pin
Type
O
I
I
I
I
I
I
P
G
NC
Pin Description
Output Modulated Frequency: Frequency modulated signal. Frequency of
the output is selected as shown in Table 1.
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It may either be connected to an external crystal, or to an
external reference clock.
Crystal Connection: Input connection for an external crystal. If using an ex-
ternal reference signal, this pin must be left unconnected.
Spread Spectrum Control (Active LOW): Asserting this signal (active LOW)
turns the internal modulation waveform on. This pin has an internal pull-down
resistor.
Modulation Width Selection: When Spread Spectrum feature is turned on,
these pins are used to select the amount of variation and peak EMI reduction
that is desired on the output signal (see Table 2).
Reference Frequency Selector: Logic level provided at this input indicates
to the internal logic what range the reference frequency is in and determines
the factor by which the device multiplies the input frequency. Refer to Table 3.
These pins have internal pull-up resistors.
Output Frequency Selection Bits: These pins select the frequency of oper-
ation for the output. Refer to Table 1. OR1: DOWN - OR2: UP.
Power Connection: Connected to 3.3V or 5V power supply.
Ground Connection: Connect all ground pins to the common ground plane.
No Connect: Leave this pin floating.
Document #: 38-07253 Rev. *A
Page 2 of 8









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W532 Даташит, Описание, Даташиты
W532
Overview
The W532 product is one of a series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer tech-
niques. By frequency modulating the output with a low fre-
quency carrier, peak EMI is greatly reduced. Use of this tech-
nology allows systems to pass increasingly difficult EMI testing
without resorting to costly shielding or redesign.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram on page 1 shows a simple implementa-
tion.
Functional Description
The W532 uses a phase-locked loop (PLL) to frequency mod-
ulate an input clock. The result is an output clock whose fre-
quency is slowly swept over a narrow band near the input sig-
nal. The basic circuit topology is shown in Figure 1. The input
reference signal is divided by Q and fed to the phase detector.
A signal from the VCO is divided by P and fed back to the
phase detector also. The PLL will force the frequency of the
VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
times the reference frequency. The unique feature of the
Spread Spectrum Frequency Timing Generator is that a mod-
ulating waveform is superimposed at the input to the VCO.
This causes the VCO output to be slowly swept across a pre-
determined frequency band.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Using frequency select bits (IR1:2, OR1:2 pins), the frequency
range can be set (see Table 1 and Table 3). Spreading per-
centage is set with pin MW as shown in Table 2.
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentages between 0.5% and 2.5% are most
common.
Clock Input
Reference Input
Freq.
Divider
Q
VDD
Phase
Detector
Charge
Pump
Σ
VCO
Post
Dividers
CLKOUT
(EMI suppressed)
Feedback
Divider
P
Modulating
Waveform
PLL
GND
Figure 1. Conceptual Block Diagram
Document #: 38-07253 Rev. *A
Page 3 of 8










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