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PDF NTB30N20 Data sheet ( Hoja de datos )
| Número de pieza | NTB30N20 | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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NTB30N20
Power MOSFET
30 Amps, 200 Volts
N−Channel Enhancement−Mode D2PAK
Features
• Source−to−Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
• Avalanche Energy Specified
• IDSS and RDS(on) Specified at Elevated Temperature
• Mounting Information Provided for the D2PAK Package
Typical Applications
• PWM Motor Controls
• Power Supplies
• Converters
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Drain−to−Source Voltage (RGS = 1.0 MΩ)
Gate−to−Source Voltage
− Continuous
− Non−Repetitive (tpv10 ms)
Drain Current
− Continuous @ TA 25°C
− Continuous @ TA 100°C
− Pulsed (Note 2)
Total Power Dissipation @ TA = 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (Note 1)
Operating and Storage Temperature Range
VDSS
VDGR
VGS
VGSM
ID
ID
IDM
PD
PD
TJ, Tstg
200 Vdc
200 Vdc
"30
"40
Vdc
Adc
30
22
90
214 W
1.43 W/°C
2.0 W
−55 to °C
+175
Single Drain−to−Source Avalanche Energy −
Starting TJ = 25°C
(VDD = 100 Vdc, VGS = 10 Vdc,
IL(pk) = 20 A, L = 3.0 mH, RG = 25 Ω)
EAS mJ
450
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient (Note 1)
RθJC
RθJA
RθJA
°C/W
0.7
62.5
50
Maximum Lead Temperature for Soldering
Purposes for 10 seconds
TL 260 °C
1. When surface mounted to an FR4 board using the minimum recommended
pad size, (Cu Area 0.412 in2).
2. Pulse Test: Pulse Width = 10 µs, Duty Cycle = 2%.
http://onsemi.com
VDSS
200 V
RDS(ON) TYP
68 mΩ @ VGS = 10 V
ID MAX
30 A
N−Channel
D
G
S
4
12
3
D2PAK
CASE 418B
STYLE 2
MARKING DIAGRAM
& PIN ASSIGNMENT
4
Drain
NTB30N20
LLYWW
1
Gate
2
Drain
3
Source
NTB30N20
LL
Y
WW
= Device Code
= Location Code
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping†
NTB30N20
NTB30N20T4
D2PAK
D2PAK
50 Units/Rail
800 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2004
April, 2004 − Rev. 3
1
Publication Order Number:
NTB30N20/D
1 page  
NTB30N20
12
10 VDS
8
6 Q1
4
2
QT
180 1000
VDD = 160 V
150 ID = 30 A
VGS = 10 V
120 100
tf
Q2
VGS 90
tr
td(off)
ID = 30 A
TJ = 25°C
60
30
10
td(on)
00
0 10 20 30 40 50 60 70
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
1
1 10
RG, GATE RESISTANCE (Ω)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
30
VGS = 0 V
25 TJ = 25°C
20
15
10
5
0
0.5 0.6
0.7 0.8
0.9
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1
Figure 10. Diode Forward Voltage versus Current
100
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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5
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