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PDF S25FL004D Data sheet ( Hoja de datos )
| Número de pieza | S25FL004D | |
| Descripción | Flash Memory | |
| Fabricantes | SPANSION | |
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S25FL Family (Serial Peripheral Interface)
S25FL004D
4 Megabit CMOS 3.0 Volt Flash Memory
with 50 Mhz SPI Bus Interface
Distinctive Characteristics
ADVANCE
INFORMATION
ARCHITECTURAL ADVANTAGES
Single power supply operation
— Full voltage range: 2.7 to 3.6 V read and program
operations
Memory Architecture
— Eight sectors with 512 Kb each
Program
— Page Program (up to 256 bytes) in 1.5 ms (typical)
— Program cycles are on a page by page basis
Erase
— 0.5 s typical sector erase time
— 4 s typical bulk erase time
Endurance
— 100,000 cycles per sector typical
Data Retention
— 20 years typical
Device ID
— Electronic signature
Process Technology
— Manufactured on 0.25 µm process technology
Package Option
— Industry Standard Pinouts
— 8-pin SO (208mil) package
— 8-contact WSON leadless package (6x5mm)
PERFORMANCE CHARACTERISTICS
Speed
— 50 MHz clock rate (maximum)
Power Saving Standby Mode
— Standby Mode 1 µA (typical)
Memory Protection Features
Memory Protection
— W# pin works in conjunction with Status Register Bits
to protect specified memory areas
— Status Register Block Protection bits (BP1, BP0) in
status register configure parts of memory as read-
only
SOFTWARE FEATURES
SPI Bus Compatible Serial Interface
Publication Number S25FL004D_00 Revision A Amendment 0 Issue Date June 28, 2004
1 page  
Advance Information
Connection Diagrams
8-pin Plastic Small Outline Package (SO)
8-contact WSON Package
CS# 1
SO 2
W#
GND
3
4
8 VCC
7 HOLD#
6 SCK
5 SI
CS#
SO
W#
GND
1
2
3
4
8 VCC
7 HOLD#
6 SCK
5 SI
Input/Output Descriptions
SCK
SI
SO
CS#
W#
HOLD#
VCC
GND
=
=
=
=
=
=
=
=
Logic Symbol
Serial Clock Input
Serial Data Input
Serial Data Output
Chip Select Input
Write Protect Input
Hold Input
Supply Voltage Input
Ground Input
VCC
SI
SCK
CS#
W#
HOLD#
GND
SO
June 28, 2004 S25FL004D_00A0
S25FL Family (Serial Peripheral Interface) S25FL004D
5
5 Page 
Advance Information
If the falling edge does not coincide with Serial Clock (SCK) being Low, the Hold
condition starts after Serial Clock (SCK) next goes Low. Similarly, if the rising
edge does not coincide with Serial Clock (SCK) being Low, the Hold condition ends
after Serial Clock (SCK) next goes Low (Figure 3). During the Hold condition, the
Serial Data Output (SO) is high impedance, and Serial Data Input (SI) and Serial
Clock (SCK) are Don’t Care.
Normally, the device remains selected, with Chip Select (CS#) driven Low, for the
entire duration of the Hold condition. This ensures that the state of the internal
logic remains unchanged from the moment of entering the Hold condition.
If Chip Select (CS#) goes High while the device is in the Hold condition, this has
the effect of resetting the internal logic of the device. To restart communication
with the device, it is necessary to drive Hold (HOLD#) High, and then to drive
Chip Select (CS#) Low. This prevents the device from going back to the Hold
condition.
SCK
HOLD#
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
Figure 3. Hold Condition Activation
June 28, 2004 S25FL004D_00A0
S25FL Family (Serial Peripheral Interface) S25FL004D
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet S25FL004D.PDF ] | |
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