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PDF S71AL016M Data sheet ( Hoja de datos )

Número de pieza S71AL016M
Descripción Stacked Multi-Chip Product (MCP) Flash Memory and RAM
Fabricantes SPANSION 
Logotipo SPANSION Logotipo



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S71AL016M Based MCPs
Stacked Multi-Chip Product (MCP) Flash Memory and
RAM
16 Megabit (1 M x 16-bit) CMOS 3.0 Volt-only
Flash Memory and 4 Megabit (256K x 16-bit) Static RAM/
Pseudo Static RAM
ADVANCE
INFORMATION
Notice to Readers: The Advance Information status indicates that this
document contains information on one or more products under development
at Spansion LLC. The information is intended to help you evaluate this product.
Do not design in this product without contacting the factory. Spansion LLC
reserves the right to change or discontinue work on this proposed product
without notice.
Publication Number S71AL016M_00 Revision A Amendment 0 Issue Date February 23, 2005

1 page




S71AL016M pdf
Advance Information
Table of Contents
S71AL016M based MCPs ............................. 3
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .6
16 Mb Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .7
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . .8
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 10
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . 11
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 12
S29AL016M .................................................13
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 13
General Description . . . . . . . . . . . . . . . . . . . . . . . . 14
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 1. S29AL016M Device Bus Operations . . . . . . . . . . . . .17
Requirements for Reading Array Data . . . . . . . . . . . . . . . . . . .17
Writing Commands/Command Sequences . . . . . . . . . . . . . . . 18
Program and Erase Operation Status . . . . . . . . . . . . . . . . . . . 18
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Automatic Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RESET#: Hardware Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 2. Sector Address Tables (Model 01, Top Boot
Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Table 3. Sector Address Tables (Model 02, Bottom Boot
Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4. Autoselect Codes (High Voltage Method) . . . . . . . . .22
Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . 22
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 1. Temporary Sector Unprotect Operation................... 23
Figure 2. In-System Single High Voltage Sector Protect/
Unprotect Algorithms ........................................................ 24
SecSi (Secured Silicon) Sector Flash Memory Region . . . . . . . 25
Table 5. SecSi Sector Addressing . . . . . . . . . . . . . . . . . . . . .25
Figure 3. SecSi Sector Protect Verify ................................... 26
Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . 26
Table 6. CFI Query Identification String . . . . . . . . . . . . . . . .27
Table 7. System Interface String . . . . . . . . . . . . . . . . . . . . .27
Table 8. Device Geometry Definition . . . . . . . . . . . . . . . . . .28
Table 9. Primary Vendor-Specific Extended Query . . . . . . . . .28
Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 30
Word Program Command Sequence . . . . . . . . . . . . . . . . . . . .31
Figure 4. Program Operation .............................................. 32
Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . 32
Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . 33
Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . 33
Figure 5. Erase Operation .................................................. 35
Program Suspend/Program Resume Command Sequence . . . 35
Figure 6. Program Suspend/Program Resume ....................... 36
Table 10. Command Definitions . . . . . . . . . . . . . . . . . . . . . .37
DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 7. Data# Polling Algorithm ....................................... 39
RY/BY#: Ready/Busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 8. Toggle Bit Algorithm............................................ 42
DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . .42
DQ3: Sector Erase Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Table 11. Write Operation Status . . . . . . . . . . . . . . . . . . . . 43
Figure 9. Maximum Negative Overshoot Waveform ............... 44
Figure 10. Maximum Positive Overshoot Waveform ............... 44
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 12. CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 11. Test Setup ....................................................... 46
Table 13. Test Specifications . . . . . . . . . . . . . . . . . . . . . . . 46
Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 12. Input Waveforms and Measurement Levels ........... 46
Table 14. Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 13. Read Operations Timings.................................... 47
Table 15. Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . 48
Figure 14. RESET# Timings ............................................... 48
Figure 15. Program Operation Timings ................................ 50
Figure 16. Chip/Sector Erase Operation Timings ................... 51
Figure 17. Data# Polling Timings
(During Embedded Algorithms) .......................................... 52
Figure 18. Toggle Bit Timings
(During Embedded Algorithms) .......................................... 52
Figure 19. DQ2 vs. DQ6 for Erase and
Erase Suspend Operations................................................. 53
Table 16. Temporary Sector Unprotect . . . . . . . . . . . . . . . . 53
Figure 20. Temporary Sector Unprotect/Timing Diagram........ 53
Figure 21. Sector Protect/Unprotect Timing Diagram............. 54
Table 17. Alternate CD# Controlled Erase/Program
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 22. Alternate CE# Controlled Write Operation T
imings ............................................................................ 56
Table 18. Erase and Programming Performance . . . . . . . . . . 57
Table 19. TSOP Pin and BGA Package Capcitance . . . . . . . . . 57
Type 4 pSRAM .......................................... 59
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Functional Description. . . . . . . . . . . . . . . . . . . . . . 59
Product Portfolio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . 60
Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 20. DC Electrical Characteristics (Over the
Operating Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . .61
AC Test Loads and Waveforms . . . . . . . . . . . . . . .61
Figure 23. AC Test Loads and Waveforms ............................ 61
Table 21. Switching Characteristics . . . . . . . . . . . . . . . . . . . 62
Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . 63
Figure 24. Read Cycle 1 (Address Transition Controlled) ........ 63
Figure 25. Read Cycle 2 (OE# Controlled)............................ 63
Figure 26. Write Cycle 1 (WE# Controlled)........................... 64
Figure 27. Write Cycle 2 (CE#1 or CE2 Controlled) ............... 65
Figure 28. Write Cycle 3 (WE# Controlled, OE# Low) ............ 66
Figure 29. Write Cycle 4 (BHE#/BLE# Controlled, OE# Low) .. 66
Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 68
February 23, 2005 S71AL016M_00_A0_A0
S71AL016M based MCPs
5

5 Page





S71AL016M arduino
Advance Information
Valid Combinations
Base Ordering
Part Number
S71AL016M40
S71AL016M40
S71AL016D Valid Combinations
Package &
Temperature
Package Modifier/
Model Number
BAW,
BFW
0B
0F
Notes:
1. Type 0 is standard. Specify other options as required.
2. BGA package marking omits leading S and packing type
designator from ordering part number.
Packing Type
Bottom-Boot
Top-Boot
Speed Options
(ns)
90
(p)SRAM
Type/Access
Time (ns)
pSRAM4/ 70
pSRAM4 / 70
Package
Marking
(Note 2)
Valid Combinations
Valid Combinations list configurations planned to be supported in vol-
ume for this device. Consult your local sales office to confirm avail-
ability of specific valid combinations and to check on newly released
combinations.
February 23, 2005 S71AL016M_0M_A0
S71AL016M
11

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