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PDF GLT6400L08 Data sheet ( Hoja de datos )
| Número de pieza | GLT6400L08 | |
| Descripción | Ultra Low Power 512k x 8 CMOS SRAM | |
| Fabricantes | G-Link | |
| Logotipo |  |
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G-LINK
GLT6400L08
Ultra Low Power 512k x 8 CMOS SRAM
Feb 2001(Rev. 1.1)
Features :
Description :
∗ Low-power consumption.
The GLT6400L08 is a low power CMOS Static
-active: 45mA at 85ns.
RAM organized as 524,288 x 8 bits. Easy memory
-stand by :
expansion is provided by an active LOW CE1 an
20 µA (CMOS input / output)
5 µA (CMOS input / output, SL)
active LOW OE , and Tri-state I/O’s. This device has
∗ Single +2.7 to 3.3V power supply.
an automatic power-down mode feature when
∗
∗
Equal access and cycle time.
85 ns access time at 2.7V to 3.3V 70ns
access time at 3V to 3.6V
deselected.
Writing to the device is accomplished by taking
chip Enable 1 ( CE1 ) with Write Enable ( WE ) LOW.
∗ 1.0V data retention mode.
Reading from the device is performed by taking Chip
∗ TTL compatible, tri-state input/output. Enable 1 ( CE1 ) with Output Enable ( OE ) LOW
∗ Automatic power-down when deselected. while Write Enable ( WE ) and Chip Enable 2 (CE2)
∗ Industrial grade (-40°C ~ 85°C)
available.
is HIGH. The I/O pins are placed in a high-impedance
state when the device is deselected : the outputs are
∗ Package available: sTSOP , SOP.
disabled during a write cycle.
The GLT6400L08 comes with a 1V data retention
feature and Lower Standby Power. The GLT6400L08
is available in a 32-pin sTSOP packages,and 32pin
SOP package.
Function Block Diagram :
INPUT BUFFER
Cell
Array
I/O7
I/O1
COLUMN DECODER
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
Column Address
-1-
CONTROL
CIRCUIT
OE
WE
CE1
CE2
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
1 page  
G-LINK
GLT6400L08
Ultra Low Power 512k x 8 CMOS SRAM
Feb 2001(Rev. 1.1)
Data Retention Waveform
Vcc
CE
2.7V
tCDR
Data Retention Mode
VDR >= 1.0V
VIH VDR
2.7V
tR
VIH
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Time
Input and Output Timing
Reference Level
0.4V to 2.4V
5 ns
1.4V
Output Load Condition
CL = 30pf + 1TTL Load
AC Test Loads and Waveforms
TTL
CL*
*Including Scope and Jig Capacitance
Read Cycle (3,9)( 70ns Vcc=3V to 3.6V , 85ns Vcc=2.7V to 3.3V )
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold from address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Power-Up Time
Power-Down Time
Symbol
tRC
tAA
tACE
tOE
tOH
tCLZ
tCHZ
tOLZ
tOHZ
tPU
tPD
70
Min Max
70
70
70
40
10
10
25
5
25
0
70
85
Unit Note
Min Max
85 ns
85 ns
85 ns
40 ns
10 ns
10 ns 4,5
35 ns 4,5
5 ns 4,5
30 ns 4,5
0 ns 5
85 ns 5
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
-5-
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet GLT6400L08.PDF ] | |
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