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HDMP-0421 PDF даташит

Спецификация HDMP-0421 изготовлена ​​​​«Hewlett-Packard» и имеет функцию, называемую «Port Bypass Circuits».

Детали детали

Номер произв HDMP-0421
Описание Port Bypass Circuits
Производители Hewlett-Packard
логотип Hewlett-Packard логотип 

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HDMP-0421 Даташит, Описание, Даташиты
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Port Bypass Circuits for Fibre
Channel Arbitrated Loop
Standard and its Extensions
Technical Data
HDMP-0421 Single
PBC & CDR
Features
• Supports ANSI X3T11
1.0625 Gbps FC-AL Loop
Configuration
• Supports 802.3z 1.25 Gbps
Gigabit Ethernet (GE) Rates
Single PBC, CDR, Dual
Signal Detect (SD) in a
Single Package
• Bidirectional, Symmetric
Bypass Capability
• CDR in Bypass Path and
Loop Path
• CDR Location Determined
by Wiring Configuration of
Pins on PCB (Patent
Pending)
• Envelope Detect on Cable
Input (SD) for Both
Directions
• Equalizers On All Inputs
• High Speed PECL I/Os
Referenced to VCC
• Buffered Line Logic (BLL)
Outputs without External
Bias Resistors
• 0.4 W Typical Power at
VCC = 3.3 V
• 5 V Tolerant LVTTL I/O
• 24 Pin SSOP Package
Applications
• RAID, JBOD Cabinets
• 1=>1 Gigabit Serial Buffer
Pair (with and w/o CDR)
• Multi-Initiator Loops
Description
The HDMP-0421 is a Single Port
Bypass Circuit (PBC) with Clock
and Data Recovery (CDR), and
dual Signal Detect (SD) capability.
This configuration will control
jitter accumulation while repeating
incoming signals. Port Bypass
Circuits are used to provide loops
that are continuously on in hard
disk arrays constructed in Fibre
Channel Arbitrated Loop (FC-AL)
configurations. Hard disks may be
pulled out or swapped while other
disks in the array are available to
the system. This device may also
be used in multi-initiator loop
configurations.
A Port Bypass Circuit is a 2:1
Multiplexer array with two modes
of operation: DISK IN LOOP and
DISK BYPASSED. In DISK IN
LOOP mode, the loop goes into
and out of the disk drive. Data go
from the HDMP-0421’s
TO_NODE[n]± differential output
pins to the Disk Drive Transceiver
IC (for example, an HDMP-1536A)
Rx± differential input pins. Data
from the Disk Drive Transceiver
IC Tx± differential output pins go
to the HDMP-0421’s
FM_NODE[n]± differential input
pins. Figures 4 and 5 show
connection diagrams for disk drive
array applications. In DISK
BYPASSED mode, the disk drive is
either absent or non-functional
and the loop bypasses the hard
disk. DISK IN LOOP mode is
enabled with a HIGH on the
BYPASS[n]– pin and DISK
BYPASSED mode is enabled with a
LOW on the same pin.
Multiple HDMP-0421s may be
cascaded or connected to other
members of the HDMP-04xx
family through the FM_LOOP and
TO_LOOP pins to create loops for
arrays of disk drives. See Table 2
to identify which of the two cells
(0:1) will provide FM_LOOP,
TO_LOOP pins (cell connected to
cable). ALL TO_NODE outputs of
the HDMP-0421 are of equal
strength. Combinations of
HDMP-04xx may be utilized to
accommodate any number of hard
disks.
The HDMP-0421 may also be used
as a pair of 1=>1 buffers, one
with a CDR and another without.
For example, HDMP-0421 may be
placed in front of a CMOS ASIC to
clean the jitter of the outgoing
signal (CDR path) and to better
read the incoming signal (CDR-
less path).









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HDMP-0421 Даташит, Описание, Даташиты
2
The design of the HDMP-0421
allows for placement of the CDR
at one of two locations with
respect to a hard disk slot. For
example, if the BYPASS[0]– pin
is HIGH and hard disk slot A is
connected to PBC cell 1, the CDR
function will be performed before
entering the hard disk at slot A
(Figure 4). To achieve a CDR
function after slot A, the
BYPASS[1]– pin must be HIGH
and hard disk slot A must be
connected to PBC cell 0
(Figure 5). Table 2 shows both
possible connections. In both
cases, a Signal Detect (SD) pin
shows the status of the signal at
the incoming cable. The
recommended method of setting
the BYPASS[i]– pins HIGH is to
drive them with a high-
impedence signal. Internal pull-
up resistors will force the
BYPASS[I]– pins to VCC.
FM_NODE[1]
FM_NODE[0]
TO_NODE[1]
LOSDET
BYPASS[1]–
1
0
SD[1]
CDR
CEXT
REFCLK
Figure 1. Block Diagram of HDMP-0421.
TO_NODE[0]
BYPASS[0]–
1
0
IOSDET
SD[0]
(1) FM_NODE[0]
(2) FM_NODE[4]
(1) TO_NODE[0]
(2) TO_NODE[0]
tdelav1.2
Figure 2. Timing Waveforms.









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HDMP-0421 Даташит, Описание, Даташиты
3
Table 1a. Truth Table for CDR at Entry Configurations
FM_LOOP = FM_NODE[0], TO_LOOP = TO_NODE[0], BYPASS[0]– = 1
TO_LOOP
FM_LOOP
FM_NODE[1]
TO_NODE[1]
FM_LOOP
FM_LOOP
BYPASS[1]–
0
1
Table 1b. Truth Table for CDR at Exit Configurations
FM_LOOP = FM_NODE[1], TO_LOOP = TO_NODE[1], BYPASS[1]– = 1
TO_LOOP
FM_LOOP
FM_NODE[0]
TO_NODE[0]
FM_LOOP
FM_LOOP
BYPASS[0]–
0
1
Table 2. Pin Connection Diagram to Achieve Desired
CDR Location (see Figures 4 and 5)
X Denotes CDR Position with respect to Hard Disks
Hard Disk
Connection to PBC Cells
CDR Position (x)
Cell Connected to Cable
A
1
xA
0
A
0
Ax
1
FM_NODE[1]–
FM_NODE[1]+
VCCHS
TO_NODE[1]–
TO_NODE[1]+
GND
GND
BYPASS[1]–
SD[1]
VCC
GND
CPLL1
1 24
2 23
3 22
4 21
5
HDMP-0421
20
6
R x.YY
19
nnnn-nnn
7
S YYWW
18
COUNTRY
8 17
9 16
10 15
11 14
12 13
FM_NODE[0]–
FM_NODE[0]+
VCCHS
TO_NODE[0]–
TO_NODE[0]+
GND
GND
BYPASS[0]–
SD[0]
VCCA
REFCLK
CPLL0
nnnn.nnn = WAFER LOT - BUILD NUMBER (1-3 DIGITS)
Rx.yy = DIE REVISION
S = SUPPLIER CODE
YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK)
COUNTRY = COUNTRY OF MANUFACTURE
Figure 3: HDMP-0421 Package Layout and Marking, Top View.










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