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HDMP-0450 PDF даташит

Спецификация HDMP-0450 изготовлена ​​​​«Hewlett-Packard» и имеет функцию, называемую «Quad Port Bypass Circuit».

Детали детали

Номер произв HDMP-0450
Описание Quad Port Bypass Circuit
Производители Hewlett-Packard
логотип Hewlett-Packard логотип 

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HDMP-0450 Даташит, Описание, Даташиты
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Agilent HDMP-0450
Quad Port Bypass Circuit
for Fibre Channel Arbitrated Loops
Data Sheet
Description
The HDMP-0450 is a Quad Port
Bypass Circuit (PBC) which
provides a low-cost, low-power
physical-layer solution for Fibre
Channel Arbitrated Loop (FC-AL)
disk array configurations. By using a
PBC such as the HDMP-0450, hard
disks may be pulled out or swapped
while other disks in the array are
available to the system.
A PBC consists of multiple 2:1
multiplexers daisy chained together.
Each port has two modes of
operation: “disk in loop” and “disk
bypassed.” When the “disk in loop”
mode is selected, the loop goes into
and out of the disk drive at that
port. For example, data goes from
the HDMP-0450’s TO_NODE[n]±
differential output pins to the Disk
Drive Transceiver IC’s (e.g., an
HDMP-1636A) Rx differential input
pins. Data from the Disk Drive
Transceiver IC’s Tx differential
outputs goes to the HDMP-0450’s
FM_NODE[n]± differential input
pins. Figure 2 shows connection
diagrams for disk drive array
applications. When the “disk
bypassed” mode is selected, the
disk drive is either absent or
nonfunctional and the loop
bypasses the hard disk.
The “disk bypassed” mode is
enabled by pulling the BYPASS[n]-
pin low. Leave BYPASS[n]-
floating to enable the “disk in
loop” mode. HDMP-0450s may be
cascaded with other members of
the HDMP-04XX/HDMP-05XX
family through the appropriate
FM_NODE[n]± and
TO_NODE[n]± pins to
accommodate any number of hard
disks (see Figure 3). The unused
cells in the HDMP-0450 may be
bypassed by using pulldown
resistors on the BYPASS[n]- pins
for these cells.
An HDMP-0450 may also be
configured as five 1:1 buffers, as
two 2:1 multiplexers, or as two
1:2 buffers.
Features
• Supports 1.0625 GBd Fibre Channel
operation
• Supports 1.25 GBd Gigabit Ethernet
(GE) operation
• Quad PBC in one package
• Signal detect on FM_NODE[0] input
• Equalizers on all inputs
• High speed LVPECL I/O
• Buffered Line Logic (BLL) outputs
(no external bias resistors required)
• 0.5 W typical power at VCC = 3.3 V
• 44 Pin, 10 mm, low-cost plastic QFP
package
Applications
• RAID, JBOD, BTS cabinets
• Two 2:1 muxes
• Two 1:2 buffers
• 1 => N gigabit serial buffer
• N => 1 gigabit serial mux
HDMP-0450
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling
and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic
discharge (ESD).









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HDMP-0450 Даташит, Описание, Даташиты
EQU
BLL
TTL
1
0
EQU
BLL
TTL
1
0
EQU
BLL
TTL
1
0
EQU
BLL
TTL
1
0
EQU
BLL
TTL
1
0
SD TTL SD
Figure 1. Block diagram of HDMP-0450.
HDMP-0450 Block Diagram
BLL OUTPUT
All TO_NODE[n]± high-speed
differential outputs are driven by
a Buffered Line Logic (BLL)
circuit that has on-chip source
termination, so no external bias
resistors are required. The BLL
outputs on the HDMP-0450 are of
equal strength and can drive in
lengthy FR-4 PCB trace.
Unused outputs should not be left
unconnected. Ideally, unused
outputs should have their
differential pins shorted together
with a short PCB trace. If longer
traces or transmission lines are
connected to the output pins, the
lines should be differentially
terminated with an appropriate
resistor. The value of the
termination resistor should match
the PCB trace differential
impedance.
EQU INPUT
All FM_NODE[n]± high-speed
differential inputs have an
Equalization (EQU) buffer to
offset the effects of skin loss and
dispersion on PCBs. An external
termination resistor is required
across all high-speed inputs. The
value of the termination resistor
should match the PCB trace
differential impedance.
Alternatively, instead of a single
resistor, two resistors in series,
with an AC ground between them,
can be connected differentially
across the FM_NODE[n]± inputs.
The latter configuration
attenuates high-frequency
common mode noise.
BYPASS[n]- INPUT
The active low BYPASS[n]- inputs
control the data flow through the
HDMP-0450. All BYPASS pins are
LVTTL and contain internal pull-
up circuitry. To bypass a port,
the appropriate BYPASS[n]- pin
should be connected to GND
through a 1 kresistor.
Otherwise, the BYPASS[n]-inputs
should be left to float, as the
internal pull-up circuitry will
force them high.
SD OUTPUT
The Signal Detect (SD) block
detects if the incoming data on
FM_NODE[0]± is valid by
examining the differential
amplitude of that input. The
incoming data is considered
valid, and SD is driven high, as
long as the amplitude is greater
than 400 mV (differential peak-to-
peak). SD is driven low as long as
the amplitude of the input signal
is less than 100 mV (differential
peak-to-peak). When the ampli-
tude of the input signal is
between 100-400 mV (differential
peak-to-peak), the SD output is
undefined.
2









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HDMP-0450 Даташит, Описание, Даташиты
HARD DISK A
HARD DISK B
HARD DISK C
HARD DISK D
SERDES
SERDES
SERDES
SERDES
EQU TTL
BLL
1
1
0
EQU TTL
BLL
1
2
0
EQU TTL
BLL
1
3
0
EQU
TTL
BLL
1
4
0
EQU
TTL
BLL
1
0
0
Figure 2. Connection diagram for Disk Array applications.
HARD DISK A
HARD DISK B
HARD DISK C
HARD DISK D
SERDES
SERDES
SERDES
SERDES
HARD DISK E
HARD DISK F
HARD DISK G
HARD DISK H
SERDES
SERDES
SERDES
SERDES
EQU TTL
BLL
1
1
0
EQU TTL
BLL
1
2
0
EQU TTL
BLL
1
3
0
EQU
TTL
BLL
1
4
0
EQU
TTL
BLL
1
0
0
EQU TTL
BLL
1
1
0
EQU TTL
BLL
1
2
0
EQU TTL
BLL
1
3
0
EQU
TTL
BLL
1
4
0
EQU TTL
BLL
1
0
0
Figure 3. Connection diagram for multiple HDMP-0450s.
3










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