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HDMP-0480 PDF даташит

Спецификация HDMP-0480 изготовлена ​​​​«Hewlett-Packard» и имеет функцию, называемую «Octal Cell Port Bypass Circuit without Clock and Data Recovery».

Детали детали

Номер произв HDMP-0480
Описание Octal Cell Port Bypass Circuit without Clock and Data Recovery
Производители Hewlett-Packard
логотип Hewlett-Packard логотип 

11 Pages
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HDMP-0480 Даташит, Описание, Даташиты
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Agilent HDMP-0480
Octal Cell Port Bypass Circuit
without Clock and Data Recovery
Data Sheet
Description
The HDMP-0480 is an Octal Cell
Port Bypass Circuit (PBC). This
device minimizes part count, cost
and jitter accumulation. Port
Bypass Circuits are used in hard
disk arrays constructed in Fibre
Channel Arbitrated Loop (FC-AL)
configurations. By using Port
Bypass Circuits, hard disks may
be pulled out or swapped while
other disks in the array are
available to the system.
A Port Bypass Circuit (PBC)
consists of multiple 2:1 multiplex-
ers daisy chained along with a
CDR. Each port has two modes of
operation: “disk in loop” and
“disk by-passed”. When the “disk
in loop” mode is selected, the loop
goes into and out of the disk drive
at that port. For example, data
goes from the HDMP-0480’s
TO_NODE[n]± differential output
pins to the Disk Drive Transceiver
IC’s (e.g. an HDMP-1636A) Rx±
differential input pins. Data from
the Disk Drive Transceiver IC’s
Tx± differential outputs goes to
the HDMP- 0480’s FM_NODE[n]±
differential input pins. When the
“disk bypassed” mode is selected,
the disk drive is either absent or
non-functional and the loop
bypasses the hard disk.
The “disk bypassed” mode is
enabled by pulling the BYPASS[n]-
pin low. Leave BYPASS[n]-
floating to enable the “disk in
loop” mode. HDMP-0480’s may be
cascaded with other members of
the HDMP-04XX/HDMP-05XX
family through the FM_NODE and
TO_NODE pins to accommodate
any number of hard disks. The
unused cells in this PBC may be
bypassed by using pulldown
resistors on the BYPASS[n]- pins
for these cells.
An HDMP-0480 may also be used
as eight 1:1 buffers. In addition,
an HDMP-0480 may be config-
ured as four 2:1 multiplexers or
as four 1:2 buffers.
Features
• Supports 1.0625 GBd fibre channel
operation
• Supports 1.25 GBd gigabit Ethernet
(GE) operation
• Octal cell PBC in one package
• Valid amplitude detection on
FM_NODE[7] input
• Equalizers on all inputs
• High speed LVPECL I/O
• Buffered Line Logic (BLL) outputs
(no external bias resistors
required)
• 0.76 W typical power at Vcc=3.3V
• 64 Pin, 10 mm, low cost plastic QFP
package
Applications
• RAID, JBOD, BTS cabinets
• Four 2:1 muxes
• Four 1:2 buffers
• 1 = > N gigabit serial buffer
• N = > 1 gigabit serial mux
HDMP-0480
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions be taken in the handling and
assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD).









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HDMP-0480 Даташит, Описание, Даташиты
12 345 670
AV
11 111 111
00 000 000
Figure 1. Block Diagram of HDMP-0480.
HDMP-0480 Block Diagram
AV Output
The Amplitude Valid (AV) block
detects if the incoming data on
FM_NODE[7]± is valid by exam-
ining the differential amplitude
of that input. The incoming data
is considered valid, and
FM_NODE[7]_AV is driven high,
as long as the amplitude is
greater than 400 mV (differential
peak-to-peak). FM_NODE[7]_AV
is driven low as long as the
amplitude of the input signal is
less than 100 mV (differential
peak-to-peak). When the ampli-
tude of the input signal is be-
tween 100-400 mV (differential
peak-to-peak), FM_NODE[7]_AV
is unpredictable.
BLL Output
All TO_NODE[n]± high-speed
differential outputs are driven by
a Buffered Line Logic (BLL)
circuit that has on-chip source
termination, so no external bias
resistors are required. The BLL
Outputs on the HDMP-0480 are of
equal strength and can drive in
excess of 120 inches of FR-4 PCB
trace. Unused outputs should not
be left unconnected. Ideally,
unused outputs should have their
differential pins shorted together
with a short PCB trace. If trans-
mission lines are connected to
the output pins, the lines should
be differentially terminated with
an appropriate resistor. The value
of the termination resistor should
match the PCB trace differential
impedance.
EQU Input
All FM_NODE[n]± high-speed
differential inputs have an
Equalization (EQU) buffer to
offset the effects of skin loss and
dispersion on PCBs. An external
termination resistor is required
across all high-speed inputs.
BYPASS[N]- Input
The active low BYPASS[n]- inputs
control the data flow through the
HDMP-0480. All BYPASS pins are
LVTTL and contain internal pull-
up circuitry. To bypass a port,
the appropriate BYPASS[n]- pin
should be connected to GND
through a 1kresistor. Other-
wise, the BYPASS[n]- inputs
should be left to float. In this
case, the internal pull-up cir-
cuitry will force them high.
2









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HDMP-0480 Даташит, Описание, Даташиты
BYPASS[7]-
GND
GND
GND
VCC
GND
GND
VCC
GND
GND
GND
GND
BYPASS[0]-
FM_NODE[7]_AV
FM_NODE[0]-
FM_NODE[0]+
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5
6
Agilent
44
43
7 HDMP-0480 42
8 41
9 nnnn-nnn Rz.zz 40
10 39
11 S YYWW 38
12 37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCCHS
TO_NODE[5]+
TO_NODE[5]-
VCCHS
TO_NODE[4]+
TO_NODE[4]-
BYPASS[4]-
FM_NODE[4]+
FM_NODE[4]-
GND
FM_NODE[3]+
FM_NODE[3]-
BYPASS[3]-
TO_NODE[3]+
TO_NODE[3]-
VCCHS
Figure 2. HDMP-0480 Package Layout and Marking, Top View.
nnnn-nnn = wafer lot - build number; Rz.zz = Die Revision; S = Supplier Code; YYWW = Date Code (YY = year, WW = work week);
COUNTRY = country of manufacture (on back side).
I/O Type Definitions
I/O Type
Definition
I-LVTTL
O-LVTTL
HS_OUT
HS_IN
C
S
LVTTL Input
LVTTL Output
High Speed Output, LVPECL Compatible
High Speed Input
External circuit node
Power supply or ground
3










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