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PDF HDMP-0482 Data sheet ( Hoja de datos )
| Número de pieza | HDMP-0482 | |
| Descripción | Octal Cell Port Bypass Circuit | |
| Fabricantes | Hewlett-Packard | |
| Logotipo |  |
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Agilent HDMP-0482
Octal Cell Port Bypass Circuit
with CDR and Data Valid Detection
Data Sheet
Description
The HDMP-0482 is an Octal Cell
Port Bypass Circuit (PBC) with
Clock and Data Recovery (CDR)
and data valid detection capabil-
ity included. This device mini-
mizes part count, cost and jitter
accumulation while repeating
incoming signals. Port Bypass
Circuits are used in hard disk
arrays constructed in Fibre
Channel Arbitrated Loop
(FC-AL) configurations. By using
Port Bypass Circuits, hard disks
may be pulled out or swapped
while other disks in the array are
available to the system.
A Port Bypass Circuit (PBC)
consists of multiple 2:1 multiplex-
ers daisy chained along with a
CDR. Each port has two modes of
operation: “disk in loop” and
“disk bypassed”. When the “disk
in loop” mode is selected, the loop
goes into and out of the disk drive
at that port. For example, data
goes from the HDMP-0482’s
TO_NODE[n]± differential output
pins to the Disk Drive Transceiver
IC’s (e.g. an HDMP-1636A) Rx±
differential input pins. Data from
the Disk Drive Transceiver IC’s
Tx± differential outputs goes to
the HDMP-0482’s FM_NODE[n]±
differential input pins. When the
“disk bypassed” mode is selected,
the disk drive is either absent or
non-functional and the loop
bypasses the hard disk.
The “disk bypassed” mode is
enabled by pulling the BYPASS[n]-
pin low. Leave BYPASS[n]-
floating to enable the “disk in
loop” mode. HDMP-0482’s may be
cascaded with other members of
the HDMP-04XX/HDMP-05XX
family through the FM_NODE and
TO_NODE pins to accommodate
any number of hard disks. The
unused cells in this PBC may be
bypassed by using pulldown
resistors on the BYPASS[n]- pins
for these cells.
An HDMP-0482 may also be used
as eight 1:1 buffers, one with a
CDR and seven without. For
example, an HDMP-0482 may be
placed in front of a CMOS ASIC
to clean the jitter of the outgoing
signal (CDR path) and to better
read the incoming signal (non-
CDR path). In addition, the
HDMP-0482 may be configured as
four 2:1 multiplexers or as four
1:2 buffers.
Features
• Supports 1.0625 GBd fibre channel
operation
• Supports 1.25 GBd Gigabit Ethernet
(GE) operation
• Octal cell PBC/CDR in one package
• CDR location determined by choice
of cable input/output
• Amplitude valid detection on
FM_NODE[7] input
• Data valid detection on
FM_NODE[0] input
– Run length violation detection
– Comma detection
– Configurable for both single-
frame and multi-frame detection
• Equalizers on all inputs
• High speed LVPECL I/O
• Buffered Line Logic (BLL) outputs
(no external bias resistors
required)
• 1.09 W typical power at Vcc=3.3V
• 64 Pin, 14 mm, low cost plastic QFP
package
Applications
• RAID, JBOD, BTS cabinets
• Four 2:1 muxes
• Four 1:2 buffers
• 1 = > N gigabit serial buffer
• N = > 1 gigabit serial mux
HDMP-0482
CAUTION: As with all semiconductor ICs, it is advised that normal static precautions
be taken in the handling and assembly of this component to prevent damage and/or
degradation which may be induced by electrostatic discharge (ESD).
1 page  
Table 1. Pin Connection Diagram to Achieve Desired CDR Location.
Hard Disk
Connection to PBC Cell
CDR Position (x)
Cell Connection to Cable
ABCDEFG
1234567
xA B C D E F G
0
ABCDEFG
01234567
AxB C D E F G
7
Hard Disk
ABCDEFG
Connection to PBC Cell
5670123
CDR Position (x)
A B C DxE F G
Cell Connection to Cable
4
x denotes CDR position with respect to hard disks.
ABCDEFG
4567012
A B C D ExF G
3
ABCDEFG
01234567
A BxC D E F G
6
ABCDEFG
3456701
A B C D E FxG
2
ABCDEFG
01234
A B CxD E F G
5
ABCDEFG
2345670
A B C D E F Gx
1
BYPASS[7]-
REFCLK
RFCM
FM_NODE[0]_DV
VCC
GND
MODE_VDD
VCCA
GND
CPLL1
CPLL0
FSEL
BYPASS[0]-
FM_NODE[7]_AV
FM_NODE[0]-
FM_NODE[0]+
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5
Agilent
44
6 43
7 HDMP-0482 42
8 41
9 nnnn-nnn Rz.zz 40
10 39
11 S YYWW 38
12 37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VCCHS
TO_NODE[5]+
TO_NODE[5]-
VCCHS
TO_NODE[4]+
TO_NODE[4]-
BYPASS[4]-
FM_NODE[4]+
FM_NODE[4]-
GND
FM_NODE[3]+
FM_NODE[3]-
BYPASS[3]-
TO_NODE[3]+
TO_NODE[3]-
VCCHS
Figure 4. HDMP-0482 Package Layout and Marking, Top View.
nnnn-nnn = wafer lot - build number; Rz.zz = Die Revision; S = Supplier Code; YYWW = Date Code
(YY = year, WW = work week); COUNTRY = country of manufacture (on back side).
Table 2. I/O Type Definitions.
I/O Type
Definition
I-LVTTL
O-LVTTL
HS_OUT
HS_IN
C
S
LVTTL Input
LVTTL Output
High Speed Output, LVPECL Compatible
High Speed Input
External circuit node
Power supply or ground
5
5 Page 
Package Information
HDMP-0482 Thermal Characteristics, TC = 0°C to 85°C, VCC = 3.15V to 3.45V
Symbol Parameter
Unit Typ. Max.
θjc
Thermal Resistance, Junction to Case °C/W
9.5
—
Note: Based on independent testing by Agilent. θja for these devices is 39.4°C/W for the HDMP-0482.
θja is measured on a standard 3x3” FR4 PCB in a still air environment. To determine the actual
junction temperature in a given application, use the following equation: Tj = TC + (θjc x PD), where TC
is the case temperature measured on the top center of the package, and PD is the power being
dissipated.
Item
Package Material
Lead Finish Material
Lead Finish Thickness
Lead Skew
Lead Coplanarity
(Seating Plane Method)
Details
Plastic
85% Tin, 15% Lead
300 – 800 micro-inches
0.20 mm max.
0.10 mm max.
PIN #1 ID
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1 48
2 47
3 46
4 45
5 44
6 43
7
8
HDMP-0482
42
41
9
TOP VIEW
40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D1
D
E1 E
A2
b
e
c
L
G
Figure 10. HDMP-0482 Package Drawing.
A
A1
Mechanical Dimensions of HDMP-0482
Dimensional Parameter
(in millmeters)
D1/E1 D/E b e L c
HDMP-0482
14.00 17.20 0.35 0.80 0.88 0.17
Tolerance
±0.10
±0.25 ±0.05 Basic +0.15/ Max
-0.10
G A2
A1 A
0.25 2.00
0.25 2.35
Max
Gage +0.10/
Plane -0.05
Max
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HDMP-0482.PDF ] | |
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