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PDF W946432AD Data sheet ( Hoja de datos )
| Número de pieza | W946432AD | |
| Descripción | DDR SDRAM | |
| Fabricantes | Winbond | |
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W946432AD
512K × 4 BANKS × 32 BITS DDR SDRAM
GENERAL DESCRIPTION
The W946432AD is a high-speed CMOS Double Data Rate synchronous dynamic random access
memory organized as 512K words x 4 banks x 32 bits.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at
the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for
WRITEs.
The W946432AD operates from a differential clock (CLK and CLK the crossing of CLK going HIGH
and CLK going LOW will be referred to as the postive edge of CLK). Commands (address and control
signals) are registered at every positive edge of CLK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well as to both edges of CLK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location
and continue for a programmed number of locations in a programmed sequence. Accesses begin with
the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command are used to select the bank and row to
be accessed. The address bits registered coincident with the READ or WRITE command are used to
select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4 or 8 locations. An
AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at
the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for
concurrent operation, thereby providing high effective bandwidth by hiding row precharge and
activation time.
FEATURES
•Double-data-rate architecture; two data transfers
per clock cycle
•Bidirectional, data strobe (DQS) is transmitted/
received with data, to be used in capturing data
at the receiver
•DQS is edge-aligned with data for READs;
center-aligned with data for WRITEs
•Differential clock inputs (CLK and CLK )
•DLL aligns DQ and DQS transitions with CLK
transitions
•Programmable DLL on or DLL off mode
• Commands entered on each positive CLK edge;
data and data mask referenced to both edges of
DQS
•Four internal banks for concurrent operation
•Data mask (DM) for write data
•Burst lengths: 2, 4, or 8
•CAS Latency: 3
•AUTO PRECHARGE option for each burst
access
•Auto Refresh and Self Refresh Modes
•15.6us Maximum Average Periodic Refresh
Interval
•2.5V (SSTL_2 compatible) I/O
•VDDQ = 2.5V ± 0.2V
•VDD = 2.5V ± 0.2V
PRELIMINARY DATA:9/8/00
1
1 page  
W946432AD
ABSOLUTE MAXIMUM RATINGS*
SYMBOL
ITEM
RATING
UNIT
VIN Input Voltage
-0.3~ VDD +0.3
V
VOUT
Output Voltage
-0.3~ VDDQ+0.3
V
VDD Power Supply Voltage
-0.3~4.6
V
VDDQ
I/O Power Supply Voltage
-0.3~3.6
V
TOPR
Operating Temperature
0~70
°C
TSTG
Storage Temperature
-55~150
°C
TSOLDER
Soldering Temperature(10s)
260 °C
PD Power Dissipation
1W
IOUT Short Circuit Output Current
50 mA
*Conditions outside the limits listed under “Absolute Maxi-mum Ratings” may cause permanent damage to the device.
NOTES
1
1
1
1
1
1
1
1
1
CAPACITANCE (VDDQ = 2.5V, VDD = 2.5 ± 0.2, f 100 MHz, TA = 25 °C)
PARMETER
Input Capacitance: CK, CK
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQ, DQS, DM
SYMBOL
Cl1
Cl2
Cl0
MIN
2.5
2.5
4.0
Note: These parameters are periodically sampled and not 100% tested.
MAX
3.5
3.5
5.5
UNITS
pF
pF
pF
NOTES
ELECTRICAL CHARACTERISTICS AND DC OPERATING CONDITIONS
(0°C ≤ TA ≤ 70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
PARAMETER/CONDITION
Supply Voltage (for devices with VDD of 2.5V)
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
INPUT LEAKAGE CURRENT
≤ ≤Any input 0V VIN VDD
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT
≤ ≤(DQs are disabled; 0V VOUT VDDQ)
OUTPUT LEVELS
Output High Current (VOUT = 1.95V)
Output Low Current (VOUT = 0.35V)
SYMBOL
VDD
VDDQ
VREF
VTT
VIH(DC)
VIL(DC)
VIN(DC)
VID(DC)
II
MIN
2.3
2.3
1.15
VREF -0.04
VREF +0.18
-0.3
-0.3
0.36
-5
IOZ -5
IOH -15.2
IOL 15.2
MAX
2.7
2.7
1.35
VREF + 0.04
VDD + 0.3
VREF -0.18
VDDQ + 0.3
VDDQ + 0.6
5
5
UNITS
V
V
V
V
V
V
V
V
NOTES
3
4
5
uA
uA
mA
mA
5 Page 
W946432AD
Burst Length
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable,
as shown in Table 1: The burst length determines the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both
the sequential and the interleaved burst types.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively
selected. All accesses for that burst take place with in this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two,
by A2-A7 when the burst length is set to four and by A3-A7 when the burst length is set to eight. The
remaining address bit is used to select the starting location within the block. The programmed burst length
applies to both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to
as the burst type and is selected by bit A3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting
column address, as shown in Table 1:.
Burst Length
2
4
8
Table 1:BURST DEFINITION
Starting Column
Address:
A1
0
0
1
1
A2 A1
00
00
01
01
10
10
11
11
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
0-1
1–0
0-1
1–0
0–1–2-3
1–2–3–0
2–3–0–1
3–0–1–2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NOTE:
1. For a burst length of two, A1-A7 selects the two-data-element block; A0 selects
the first access within the block.
2. For a burst length of four, A2-A7 selects the four-data-element block; A0-A1
selects the first access within the block.
3. For a burst length of eight, A3-A7 selects the eight-data- element block; A0-A2
selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
11
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