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PDF HLX6256 Data sheet ( Hoja de datos )
| Número de pieza | HLX6256 | |
| Descripción | 32K x 8 STATIC RAM-Low Power SOI | |
| Fabricantes | Honeywell | |
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Military & Space Products
32K x 8 STATIC RAM—Low Power SOI
HLX6256
FEATURES
RADIATION
• Fabricated with RICMOS™ IV Silicon on Insulator (SOI)
0.55 µm Low Power Process
• Total Dose Hardness through 1x106 rad(SiO2)
• Neutron Hardness through 1x1014 cm-2
• Dynamic and Static Transient Upset Hardness
through 1x109 rad(Si)/s
• Dose Rate Survivability through 1x1011 rad(Si)/s
• Soft Error Rate of <1x10-10 upsets/bit-day
• Latchup Free
OTHER
• Read/Write Cycle Times
≤ 17 ns (Typical)
≤ 25 ns (-55 to 125°C)
• Typical Operating Power <10 mW/MHz
• Asynchronous Operation
• JEDEC Standard Low Voltage
CMOS Compatible I/O
• Single 3.3 V ± 0.3V Power Supply
• Packaging Options
- 28-Lead Flat Pack (0.500 in. x 0.720 in.)
- 28-Lead DIP, MIL-STD-1835, CDIP2-T28
- 36-Lead Flat Pack (0.630 in. x 0.650 in.)
- Various Multi-Chip Module (MCM) Configurations
GENERAL DESCRIPTION
The 32K x 8 Radiation Hardened Static RAM is a high
performance 32,768 word x 8-bit static random access
memory with industry-standard functionality. It is fabri-
cated with Honeywell’s radiation hardened technology,
and is designed for use in low voltage systems operating in
radiation environments. The RAM operates over the full
military temperature range and requires only a single 3.3 V
± 0.3V power supply. The RAM is compatible with JEDEC
standard low voltage CMOS I/O. Power consumption is
typically less than 10 mW/MHz in operation, and less than
2 mW when de-selected. The RAM read operation is fully
asynchronous, with an associated typical access time of 14
ns at 3.3 V.
Honeywell’s enhanced SOI RICMOS™IV (Radiation Insen-
sitive CMOS) technology is radiation hardened through the
use of advanced and proprietary design, layout and pro-
cess hardening techniques. The RICMOS™ IV low power
process is a SIMOX CMOS technology with a 150 Å gate
oxide and a minimum drawn feature size of 0.7 µm (0.55 µm
effective gate length—Leff). Additional features include
tungsten via plugs, Honeywell’s proprietary SHARP pla-
narization process and a lightly doped drain (LDD) struc-
ture for improved short channel reliability. A 7 transistor
(7T) memory cell is used for superior single event upset
hardening, while three layer metal power bussing and the
low collection volume SIMOX substrate provide improved
dose rate hardening.
1 page  
HLX6256
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
IDDSB1 Static Supply Current
IDDSBMF Standby Supply Current - Deselected
IDDOPW Dynamic Supply Current, Selected (Write)
IDDOPR Dynamic Supply Current, Selected (Read)
II Input Leakage Current
IOZ Output Leakage Current
VIL Low-Level Input Voltage
VIH High-Level Input Voltage
VOL
Low-Level Output Voltage
Typical Worst Case (2)
(1) Min Max
Units
1.0 mA
1.0 mA
3.0 mA
3.0 mA
-1 +1 µA
-1 +1 µA
-0.3 0.3xVDD V
V
Test Conditions
VIH=VDD IO=0
VIL=VSS Inputs Stable
NCS=VDD, IO=0,
f=40 MHz
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS
f=1 MHz, IO=0, CE=VIH=VDD
NCS=VIL=VSS
VSS≤VI≤VDD
VSS≤VIO≤VDD
Output=high Z
March Pattern
VDD = 3.0V
0.7xVDD VDD+.3
V
V
March Pattern
VDD = 3.6V
0.4 V VDD = 3.0V, IOL = 8 mA
VOH
High-Level Output Voltage
2.7 V VDD = 3.0V, IOH = -4 mA
(1) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.
(2) Worst case operating conditions: VDD=3.0 V to 3.6 V, TA=-55°C to +125°C, post total dose at 25°C.
(3) All inputs switching. DC average current.
DUT
output
2.2 V
249Ω
+
Vref1 -
Vref2 +
-
Valid high
output
Valid low
output
CL >50 pF*
*CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ
Tester Equivalent Load Circuit
5
5 Page 
36-LEAD FLAT PACK (22018131-001)
E
1 22018131-001
HLX6256
Top
View
H
J
L
Ceramic
Body
A
L
Kovar
Lid [3]
I
CX
Optional
N
VSS
VDD
Capacitors VDD VSS
Y
1
OV
W
T
P
R
U
b
(width)
e
(pitch)
Non-
Conductive
Tie-Bar
0.004
M
All dimensions are in inches [1]
A 0.095 ± 0.014
M 0.008 ± 0.003
S b 0.008 ± 0.002
C 0.005 to 0.0075
N 0.050 ± 0.010
O 0.090 ref
D 0.650 ± 0.010
P 0.015 ref
E 0.630 ± 0.007
R 0.075 ref
e 0.025 ± 0.002 [2] S 0.113 ± 0.010
F 0.425 ± 0.005 [2] T 0.050 ref
G 0.525 ± 0.005
U 0.030 ref
H 0.135 ± 0.005
V 0.080 ref
I 0.030 ± 0.005
W 0.005 ref
J 0.080 typ.
X 0.450 ref
L 0.285 ± 0.015
Y 0.400 ref
[1] Parts delivered with leads unformed
[2] At tie bar
[3] Lid tied to VSS
DYNAMIC BURN-IN DIAGRAM*
F16 R 1 A14
F7 R 2 A12
F6 R 3 A7
F5 R 4 A6
F4 R 5 A5
F3 R 6 A4
F2 R 7 A3
F8 R 8 A2
F13 R 9 A1
F14 R 10 A0
F1 R 11 DQ0
F1 R 12 DQ1
F1 R 13 DQ2
VSS
14 VSS
VDD 28
NWE 27
A13 26
A8 25
A9 24
A11 23
NOE 22
A10 21
NCS 20
DQ7 19
DQ6 18
DQ5 17
DQ4 16
DQ3 15
VDD
R F0
R F15
R F12
R F11
R F10
R F17
R F9
R F17
R F1
R F1
R F1
R F1
R F1
VDD = 3.9V, R ≤ 10 KΩ, VIH = VDD, VIL = VSS
Ambient Temperature ≥ 125 °C, F0 ≥ 100 KHz Sq Wave
Frequency of F1 = F0/2, F2 = F0/4, F3 = F0/8, etc.
STATIC BURN-IN DIAGRAM*
VDD
R
R
R
R
R
R
R
R
R
R
R
R
R
VSS
1 A14
2 A12
3 A7
4 A6
5 A5
6 A4
7 A3
8 A2
9 A1
10 A0
11 DQ0
12 DQ1
13 DQ2
14 VSS
VDD 28
NWE 27
A13 26
A8 25
A9 24
A11 23
NOE 22
A10 21
NCS 20
DQ7 19
DQ6 18
DQ5 17
DQ4 16
DQ3 15
VDD
R
R
R
R
R
R
R
R
R
R
R
R
R
R
VDD = 3.6V min., R ≤ 10 KΩ
Ambient Temperature ≥ 125 °C
*36-lead Flat Pack burn-in diagram has similar connections and is available on request.
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet HLX6256.PDF ] | |
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