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PDF HMN1288J Data sheet ( Hoja de datos )
| Número de pieza | HMN1288J | |
| Descripción | Non-Volatile SRAM MODULE 1Mbit | |
| Fabricantes | Hanbit | |
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HANBit
HMN1288J
Non-Volatile SRAM MODULE 1Mbit (128K x 8-Bit),34Pin-JLCC, 5V
Part No. HMN1288J
GENERAL DESCRIPTION
The HMN1288J Nonvolatile SRAM is a 1,048,576-bit static RAM organized as 131,072 bytes by 8 bits.
The HMN1288J has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write
cycles of standard SRAM and integral control circuitry which constantly monitors the single 5V supply for an out-of-
tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the
memory until after Vcc returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the
SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is
switched on to sustain the memory until after VCC returns valid.
The HMN1288J uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide non-
volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.
FEATURES
w Access time : 55, 70 ns
w High-density design : 4Mbit Design
w Battery internally isolated until power is applied
w Industry-standard 34-pin 128K x 8 pinout
w Unlimited write cycles
w Data retention in the absence of VCC
w 10-years minimum data retention in absence of power
w Automatic write-protection during power-up/power-down
cycles
w Data is automatically protected during power loss
w Conventional SRAM operation; unlimited write cycles
/NBW
A(15)
A(16)
/RST
VCC
/WE
/OE
/CE
D(7)
D(6)
D(5)
D(4)
D(3)
D(2)
D(1)
D(0)
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PIN ASSIGNMENT
JLCC
TOP VIEW
34 NC
33 NC
32 A(14)
31 A(13)
30 A(12)
29 A(11)
28 A(10)
27 A(9)
26 A(8)
25 A(7)
24 A(6)
23 A(5)
22 A(4)
21 A(3)
20 A(2)
19 A(1)
18 A(0)
OPTIONS
w Timing
55 ns
70 ns
MARKING
-55
-70
URL: www.hbe.co.kr
Rev.0.0 (FEBRUARY/ 2002)
1 HANBit Electronics Co.,Ltd.
1 page  
HANBit
HMN1288J
WRITE CYCLE (TA= TOPR, Vccmin £ Vcc ≤ Vccmax )
PARAMETER
SYMBOL CONDITIONS
-70
MIN MAX
-85
MIN MAX
UNIT
Write Cycle Time
tWC
55 - 70 - ns
Chip enable to end of write tCW Note 1 45 - 60 - ns
Address setup time
tAS Note 2 0 - 0 - ns
Address valid to end of write tAW Note 1 45 - 60 - ns
Write pulse width
tWP Note 1 40 - 50 - ns
Write recovery time (write cycle 1)
tWR1
Note 3
5
-
5
- ns
Write recovery time (write cycle 2)
tWR2
Note 3
15
-
15
-
ns
Data valid to end of write
tDW
20 - 25 - ns
Data hold time (write cycle 1) tDH1 Note 4 0 - 0 - ns
Data hold time (write cycle 2) tDH2 Note 4 0 - 0 - ns
Write enabled to output in high Z
tWZ
Note 5
0 20 0 25 ns
Output active from end of write
tOW
Note 5
5
-
5
- ns
NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE
going low and /WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high-
impedance state.
TIMING WAVEFORM
- READ CYCLE NO.1 (Address Access)*1,2
Address
DOUT
tRC
tACC
tOH
Previous Data Valid
Data Valid
- READ CYCLE NO.2 (/CE Access)*1,3,4
/CE
DOUT
tCLZ
High-Z
URL: www.hbe.co.kr
Rev.0.0 (FEBRUARY/ 2002)
tACE
tRC
5
tCHZ
High-Z
HANBit Electronics Co.,Ltd.
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet HMN1288J.PDF ] | |
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