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PDF HMN4M8DN Data sheet ( Hoja de datos )
| Número de pieza | HMN4M8DN | |
| Descripción | Non-Volatile SRAM MODULE 32Mbit | |
| Fabricantes | Hanbit Electronics | |
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HANBit
HMN4M8DV(N)
Non-Volatile SRAM MODULE 32Mbit (4,096K x 8-Bit), 40Pin-DIP, 3.3V
Part No. HMN4M8DV(N)
GENERAL DESCRIPTION
The HMN4M8DV Nonvolatile SRAM is a 33,554,432-bit static RAM organized as 4,194,304 bytes by 8 bits.
The HMN4M8DV has a self-contained lithium energy source provide reliable non -volatility coupled with the unlimited write
cycles of standard SRAM and integral control circuitry which constantly monitors the single 3.3V supply for an out-of-
tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the
memory until after VCC returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the
SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source
is switched on to sustain t he memory until after VCC returns valid.
The HMN4M8DV uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide non -
volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.
FEATURES
w Access time : 55, 70ns
w High-density design : 32Mbit
Design
w Battery internally isolated until
power is applied
w Industry-standard 40-pin 4,096K
x 8 pinout
w Unlimited write cycles
w Data retention in the absence of
VCC
w 5-years minimum data retention
in absence of power
w Automatic write-protection during
power-up/power-down cycles
w Data is automatically protected
during power loss
PIN ASSIGNMENT
A21 1
A20 2
A18 3
A16 4
A14 5
A12 6
A7 7
A6 8
A5 9
A4 10
A3 11
A2 12
A1 13
A0 14
DQ0 15
DQ1 16
DQ2 17
VSS 18
NC 1
36 VCC A21 2
35 A19 A20 3
34 NC A18 4
33 A15 A16 5
32 A17 A14 6
31 /WE A12 7
30 A13 A7 8
29 A8
A6 9
28 A9
A5 10
27 A11 A4 11
26 /OE A3 12
25 A10 A2 13
24 /CE A1 14
23 DQ7 A0 15
22 DQ6 DQ0 16
21 DQ5 DQ1 17
20 DQ4 DQ2 18
19 DQ3 VSS 19
NC 20
40 NC
39 VCC
38 A19
37 NC
36 A15
35 A17
34 /WE
33 A13
32 A8
31 A9
30 A11
29 /OE
28 A10
27 /CE
26 DQ7
25 DQ6
24 DQ5
23 DQ4
22 DQ3
21 NC
36-pin Encapsulated Package
40-pin Encapsulated Package
w Package Option
- HMN4M8DV
- HMN4M8DVN
- 36 Pin DIP Package
- 40 Pin DIP Package
URL : www.hbe.co.kr
Rev. 1.0 (May, 2002)
1 HANBit Electronics Co.,Ltd
1 page  
HANBit
HMN4M8DV(N)
READ CYCLE (TA= TOPR, VCCmin £ VCC≤ VCCmax )
PARAMETER
SYMBOL CONDITIONS
-70
MIN MAX
Read Cycle Time
tRC
70 -
Address Access Time
tACC Output load A - 70
Chip enable access time
tACE Output load A - 70
Output enable to Output valid
tOE Output load A - 35
Chip enable to output in low Z
tCLZ
Output load B
5
-
Output enable to output in low Z
tOLZ
Output load B
5
-
Chip disable to output in high Z
tCHZ Output load B 0 25
Output disable to output high Z
tOHZ Output load B 0 25
Output hold from address change
tOH
Output load A 10
-
-85
MIN MAX
85 -
- 85
- 85
- 45
5-
0-
0 35
0 25
10 -
-120
MIN MAX
120 -
- 120
- 120
- 60
5-
0-
0 45
0 35
10 -
-150
MIN MAX
150 -
- 150
- 150
- 70
10 -
5-
0 60
0 50
10 -
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE (TA= TOPR, Vccmin £ Vcc ≤ Vccmax )
PARAMETER
SYMBOL CONDITIONS
-70 -85 -120
MIN MAX MIN MAX MIN MAX
-150
Min Max
Write Cycle Time
tWC
70 - 85 - 120 - 150 -
Chip enable to end of write
tCW
Note 1
65 - 75 - 100 - 100 -
Address setup time
tAS
Note 2
0-0-0-0-
Address valid to end of write
tAW
Note 1
65 - 75 - 100 - 90 -
Write pulse width
tWP
Note 1
55 - 65 - 85 - 90 -
Write recovery time (write cycle 1)
tWR1
Note 3
5-5-5-5-
Write recovery time (write cycle 2)
tWR2
Note 3
15 - 15 - 15 - 15 -
Data valid to end of write
tDW
30 - 35 - 45 - 50 -
Data hold time (write cycle 1)
tDH1
Note 4
0-0-0-0-
Data hold time (write cycle 2)
tDH2
Note 4
10 - 10 - 10 - 0 -
Write enabled to output in high Z
tWZ
Note 5
0 25 0 30 0 40 0 50
Output active from end of write
tOW
Note 5
5-0-0-5-
NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at t he later transition of /CE
going low and /WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outpu ts remain in high-
impedance state.
UNI
T
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
URL : www.hbe.co.kr
Rev. 1.0 (May, 2002)
5 HANBit Electronics Co.,Ltd
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HMN4M8DN.PDF ] | |
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