DataSheet.es    


PDF HMN5128D Data sheet ( Hoja de datos )

Número de pieza HMN5128D
Descripción Non-Volatile SRAM MODULE 4Mbit
Fabricantes Hanbit Electronics 
Logotipo Hanbit Electronics Logotipo



Hay una vista previa y un enlace de descarga de HMN5128D (archivo pdf) en la parte inferior de esta página.


Total 9 Páginas

No Preview Available ! HMN5128D Hoja de datos, Descripción, Manual

www.DataSheet4U.com
HANBit
HMN5128D
Non-Volatile SRAM MODULE 4Mbit (512K x 8-Bit),32Pin-DIP, 5V
Part No. HMN5128D
GENERAL DESCRIPTION
The HMN5128D Nonvolatile SRAM is a 4,194,304-bit static RAM organized as 524,288 bytes by 8 bits.
The HMN5128D has a self-contained lithium energy source provide reliable non-volatility coupled with the unlimited write
cycles of standard SRAM and integral control circuitry which constantly monitors the single 5V supply for an out-of-
tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on to sustain the
memory until after Vcc returns valid and write protection is unconditionally enabled to prevent garbled data. In addition the
SRAM is unconditionally write-protected to prevent an inadvertent write operation. At this time the integral energy source is
switched on to sustain the memory until after VCC returns valid.
The HMN5128D uses extremely low standby current CMOS SRAMs, coupled with small lithium coin cells to provide non-
volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.
FEATURES
w Access time : 70, 85,120, 150 ns
w High-density design : 4Mbit Design
w Battery internally isolated until power is applied
w Industry-standard 32-pin 512K x 8 pinout
w Unlimited write cycles
w Data retention in the absence of VCC
w 10-years minimum data retention in absence of power
w Automatic write-protection during power-up/power-down
cycles
w Data is automatically protected during power loss
w Conventional SRAM operation; unlimited write cycles
OPTIONS
w Timing
70 ns
85 ns
120 ns
150 ns
MARKING
-70
-85
-120
-150
PIN ASSIGNMENT
A18 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
DQ0 13
DQ1 14
DQ2 15
VSS 16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin Encapsulated Package
VCC
A15
A17
/WE
A13
A8
A9
A11
/OE
A10
/CE
DQ7
DQ6
DQ5
DQ4
DQ3
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
1 HANBit Electronics Co.,Ltd

1 page




HMN5128D pdf
HANBit
HMN5128D
READ CYCLE (TA= TOPR, VCCmin £ VCCVCCmax )
PARAMETER
SYMBOL CONDITIONS
-70
-85
-120
-150
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
Read Cycle Time
tRC
70 - 85 - 120 - 150 -
ns
Address Access Time
tACC Output load A - 70 - 85 - 120 - 150 ns
Chip enable access time
tACE Output load A - 70 - 85 - 120 - 150 ns
Output enable to Output valid
tOE Output load A - 35 - 45 - 60 - 70 ns
Chip enable to output in low Z
tCLZ
Output load B
5
-
5
-
5
- 10 -
ns
Output enable to output in low Z
tOLZ
Output load B
5
-
0
-
0
-
5
-
ns
Chip disable to output in high Z
tCHZ Output load B 0 25 0 35 0 45 0 60 ns
Output disable to output high Z
tOHZ Output load B 0 25 0 25 0 35 0 50 ns
Output hold from address change
tOH
Output load A 10 - 10 - 10 - 10 -
ns
WRITE CYCLE (TA= TOPR, Vccmin £ Vcc Vccmax )
PARAMETER
SYMBOL CONDITIONS
-70
MIN MAX
-85
MIN MAX
-120
MIN MAX
-150
Min Max
Write Cycle Time
tWC
70 - 85 - 120 - 150 -
Chip enable to end of write
tCW
Note 1
65 - 75 - 100 - 100 -
Address setup time
tAS
Note 2
0-0-0-0-
Address valid to end of write
tAW
Note 1
65 - 75 - 100 - 90 -
Write pulse width
tWP
Note 1
55 - 65 - 85 - 90 -
Write recovery time (write cycle 1)
tWR1
Note 3
5-5-5-5-
Write recovery time (write cycle 2)
tWR2
Note 3
15 - 15 - 15 - 15 -
Data valid to end of write
tDW
30 - 35 - 45 - 50 -
Data hold time (write cycle 1)
tDH1
Note 4
0-0-0-0-
Data hold time (write cycle 2)
tDH2
Note 4
10 - 10 - 10 - 0 -
Write enabled to output in high Z
tWZ
Note 5
0 25 0 30 0 40 0 50
Output active from end of write
tOW
Note 5
5-0-0-5-
NOTE: 1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE
going low and /WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high-
impedance state.
UNI
T
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
5 HANBit Electronics Co.,Ltd

5 Page










PáginasTotal 9 Páginas
PDF Descargar[ Datasheet HMN5128D.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
HMN5128DNon-Volatile SRAM MODULE 4MbitHanbit Electronics
Hanbit Electronics
HMN5128DVNon-Volatile SRAM MODULE 4MbitHanbit Electronics
Hanbit Electronics
HMN5128JVNon-Volatile SRAM MODULE 4MbitHanbit Electronics
Hanbit Electronics

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar