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PDF HMNR1288D Data sheet ( Hoja de datos )
| Número de pieza | HMNR1288D | |
| Descripción | TIMEKEEPER NVSRAM | |
| Fabricantes | Hanbit Electronics | |
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HANBit
HMNR1288D(V)
5.0 or 3.3V, 1 Mbit (128 Kbit x 8) TIMEKEEPER NVSRAM
Part No. HMNR1288D(V)
GENERAL DESCRIPTION
The HMNR1288D(V) TIMEKEEPER SRAM is a 128Kb x 8 non-volatile static RAM and real time clock organized as
131,072 words by 8 bits. The special DIP package provides a fully integrated battery back-up memory and real time clock
solution. The HMNR1288D(V) directly replaces industry standard 128Kbit x 8 SRAMs. It also provides the non-volatility of
Flash without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed.
FEATURES
■ YEAR 2000 COMPLIANT
■ INTEGRATED LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, BATTERY and
CRYSTAL
■ BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS
■ AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION VOLTAGES :
(VPFD = Power-fail Deselect Voltage)
– HMNR1288D : VCC = 4.5 to 5.5V
4.2V ≤ VPFD ≤ 4.5V
– HMNR1288DV: VCC = 3.0 to 3.6V
2.7V ≤ VPFD ≤ 3.0V
■ CONVENTIONAL SRAM OPERATION : UNLIMITED WRITE CYCLES
■ SOFTWARE CONTROLLED CLOCK CALIBRATION FOR HIGH ACCURACY APPLICATIONS
■ 10 YEARS OF DATA RETENTION and CLOCK OPERATION IN THE ABSENCE OF POWER PIN and FUNCTION
COMPATIBLE WITH INDUSTRY STANDARD 128K x 8 SRAMS
■ SELF-CONTAINED BATTERY and CRYSTAL IN DIP PACKAGE
■ BATTERY LOW WARNING FLAG
■ SOFTWARE CONTROLLED CLOCK CALIBRATION
FOR HIGH ACCURACY APPLICATIONS
■ MICROPROCESSOR POWER-ON RESET
PIN ASSIGNMENT
(Valid even during battery back-up mode)
■ PROGRAMMABLE ALARM OUTPUT ACTIVE IN
BATTERY BACK-UP MODE
OPTIONS
w Timing
70 ns
85 ns
MARKING
-70
-85
/RST
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 A15
30 IRQ/FT
29 /WE
28 A13
27 A8
26 A9
25 A11
24 /OE
23 A10
22 /CE
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
32-pin Encapsulated Package
URL : www.hbe.co.kr
Rev. 1.0 (April, 2002)
1 HANBit Electronics Co.,Ltd
1 page  
HANBit
HMNR1288D(V)
OPERATING MODES
The 32-pin, 600mil DIP Hybrid houses a controller chip, SRAM, quartz crystal, and a long life lithium button cell in a single
package. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year-compliant until the year 2100), 30, and 31 day months are made automatically. Byte
1FFF8h is the clock control register. This byte controls u ser access to the clock information and also stores the clock
calibration setting. The seven clock bytes (1FFFFh-1FFF9h) are not the actual clock counters, they are memory locations
consisting of READ/WRITE memory cells within the static RAM array. The HMNR1288D(V) includes a clock control circuit
which updates the clock bytes with current information once per second. The information can be accessed by the user in
the same manner as any other location in the static memory array. The HMNR1288D(V) also has its own Power-Fail
Detect circuit. This control circuitry constantly monitors the supply voltage for an out of tolerance condition.
When VCC is out of tolerance, the circuit write protects the TIMEKEEPER register data and SRAM, providing data security
in the midst of unpredictable system operation. As VCC falls, the control circuitry automatically switches to the battery,
maintaining data and clock operation until valid power is restored.
Operating Modes
Mode
VCC
/CE /OE /WE DQ7 – DQ0
Power
Deselect
WRITE
READ
READ
Deselect
4.5V to 5.5V
or
3.0V to 3.6V
VSO to VPFD (min)
VIH X
VIL X
VIL VIL
VIL VIH
XX
Deselect
≤ VSO (1)
XX
Note : X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
X
VIL
VIH
VIH
X
X
High-Z
DIN
DOUT
High
High
High
Standby
Active
Active
Active
CMOS
Standby
Battery Back-
up
READ Mode
The HMNR1288D(V) is in the READ Mode whenever /WE (WRITE Enable) is high and /CE (Chip Enable) is low. The
unique address specified by the 17 Address Inputs defines which one of the 131,072 bytes of data is to be accessed. Valid
data will be available at the Data I/O pins within Address Access Time (tAVQV) after the last address input signal is stable,
providing the /CE and /OE access times are also satisfied. If the /CE and /OE access times are not met, valid data will be
available after the latter of the Chip Enable Access Times (tELQV) or Output Enable Access Time (tGLQV). The state of the
eight three-state Data I/O signals is controlled by /CE and /OE. If the outputs are activated before tAVQV, the data lines will
be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while /CE and /OE remain active, output
data will remain valid for Output Data Hold Time ( tAXQX) but will go indeterminate until the next Address Access.
Figure 2. READ Mode AC Waveforms
/CE
/OE
Note : /WE = High.
URL : www.hbe.co.kr
Rev. 1.0 (April, 2002)
5 HANBit Electronics Co.,Ltd
5 Page 
HANBit
Figure 7. Back-up Mode Alarm Waveforms
HMNR1288D(V)
Watchdog Timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by
setting the desired amount of time-out into the Watchdog Register, address 1FFF7h. Bits BMB4-BMB0 store a binary
multiplier and the two lower order bits RB1-RB0 select the resolution, where 00 = 1/16 second, 01 = 1/4 sec -ond, 10 = 1
second, and 11 = 4 seconds. The amount of time-out is then determined to be the multiplication of the five-bit multiplier
value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is a function of the selected resolution. If the processor does not reset the timer within the
specified period, the HMNR1288D(V) sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a
microprocessor reset. WDF is reset by reading the Flags Register (Address 1FFF0h). The most significant bit of the
Watchdog Register is the Watchdog Steering Bit (WDS). When set to a ’0,’the watchdog will activate the IRQ/FT pin when
timed-out. When WDS is set to a ’1,’the watchdog will output a negative pulse on the RST pin for 40 to 200 ms. The
Watchdog register and the FT Bit will reset to a ’0’at the end of a Watchdog time-out
when the WDS Bit is set to a ’1.’The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be applied to the Watchdog Input pin (WDI);
2. the microprocessor can perform a WRITE of the Watchdog Register. The time-out period then starts over. The
WDI pin should be tied to VSS if not used. The watchdog will be reset on each transition (edge) se en by the WDI
pin. In the order to perform a software reset of the watchdog timer, the original time -out period can be written into
the Watchdog Register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the
WDS Bit is programmed to output an interrupt, a value of “00h”needs to be written to the Watchdog Register in
order to clear the IRQ/FT pin. This will also disable the watchdog function until it is again programmed correctly.
A READ of the Flags Register will reset the Watchdog Flag (Bit D7; Register 1FFF0h).
The watchdog function is automatically disabled upon power-down and the Watchdog Register is cleared. If the watchdog
function is set to output to the IRQ/FT pin and the frequency test function is activated, the watchdog or alarm function
prevails and the frequency test function is denied.
Power-on Reset
The HMNR1288D(V) continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open
drain) and remains low on power-up for tREC after VCC passes VPFD (max). The RST pin is an open drain output and an
appro-priate pull-up resistor to VCC should be chosen to control the rise time.
Initial Power-on Defaults
Upon application of power to the device, the following register bits are set to a ’0’state: WDS, BMB0-BMB4, RB0,RB1,
AFE, ABE, W, R and FT.
URL : www.hbe.co.kr
Rev. 1.0 (April, 2002)
12 HANBit Electronics Co.,Ltd
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet HMNR1288D.PDF ] | |
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