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PDF AD7982 Data sheet ( Hoja de datos )
| Número de pieza | AD7982 | |
| Descripción | 1 MSPS PulSAR ADC | |
| Fabricantes | Analog Devices | |
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18-bit, 1 MSPS PulSAR™ ADC in MSOP/QFN
Preliminary Technical Data
18-bit resolution with no missing codes
Throughput: 1MSPS
Low Power dissipation: 7.5 mW @ 1MSPS, 75 μW @ 10kSPS
INL: ±1 LSB typ, ±2.5 LSB max
Dynamic range: 99 dB
True differential analog input range: ±VREF
0 V to VREF with VREF between 2.5V to 5.0V
Any input range and easy to drive with the ADA4941
No pipeline delay
Single-supply 2.5V operation with 1.8 V/2.5 V/3 V/5 V logic
interface
Serial interface SPI®/QSPI™/MICROWIRE™/DSP-compatible
Daisy-chain multiple ADCs and BUSY indicator
10-lead package: MSOP (MSOP-8 size) and
QFN (LFCSP), 3 mm × 3 mm same space as SOT-23
APPLICATIONS
Battery-powered equipment
Data acquisitions
Instrumentation
Medical instruments
Seismic Data Acquisition Systems
Table 1. MSOP, QFN(LFCSP)/SOT-23 14, 16 and18-Bit ADC
Type
100
kSPS
250
kSPS
400-
500
kSPS
1000
kSPS
ADC
Driver
18Bit
AD76911 AD76901 AD79821 ADA4941
ADA4841
16Bit AD7680 AD76851 AD76861 AD79801 ADA4941
AD7683 AD76871 AD76881
ADA4841
AD7684 AD7694 AD76931
14Bit AD7940 AD79421 AD79461
1 Pin-for-pin compatible.
AD7982
APPLICATION DIAGRAM EXAMPLE
2.5 TO 5V 2.5V
±10V, ±5V, ..
ADA4941
REF VDD VIO
IN+ SDI
AD7982 SCK
IN–
GND
SDO
CNV
1.8 TO 5V
3- OR 4-WIRE
INTERFACE
(SPI, , CS
DAISY CHAIN)
Figure 1.
GENERAL DESCRIPTION
The AD7982 is a 18-bit, successive approximation, analog-to-
digital converter (ADC) that operates from a single power
supply, VDD. It contains a low power, high speed, 18-bit
sampling ADC and a versatile serial interface port. On the CNV
rising edge, it samples the voltage difference between IN+ and
IN− pins. The voltages on these pins usually swing in opposite
phase between 0 V and REF. The reference voltage, REF, is
applied externally and can be set independently of the supply
voltage, VDD.
Its power scales linearly with throughput.
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy chain several ADCs on a single,
3-wire bus and provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
The AD7982 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
Rev PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
Preliminary Technical Data
AD7982
TIMING SPECIFICATIONS
−40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise stated.
Table 4. 1
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width ( CS Mode )
SCK Period ( CS Mode or Chain mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.7 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
VIO Above 1.7 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 3 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with BUSY indicator)
1 See Figure 2 and Figure 3 for load conditions.
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
Min Typ Max Unit
350 750 ns
250 ns
1000
ns
10 ns
ns
10 ns
10.5 ns
11.5 ns
12.5 ns
14.5 ns
3 ns
3 ns
3 ns
7.5 ns
8 ns
9 ns
10 ns
13 ns
10 ns
15 ns
15 ns
15 ns
0 ns
5 ns
5 ns
2.5 ns
3 ns
15 ns
Rev PrC | Page 5 of 23
5 Page 
Preliminary Technical Data
Transfer Functions
The ideal transfer characteristic for the AD7982 is shown in
Figure 12 and Table 7.
011...111
011...110
011...101
AD7982
TYPICAL CONNECTION DIAGRAM
Figure 13 shows an example of the recommended connection
diagram for the AD7982 when multiple supplies are available.
100...010
100...001
100...000
–FS
–FS + 1 LSB
–FS + 0.5 LSB
+FS – 1 LSB
+FS – 1.5 LSB
ANALOG INPUT
Figure 12. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Description
FSR – 1 LSB
Analog Input
VREF = 5 V
+4.999962 V
Digital Output Code Hexa
1FFFF1
Midscale + 1 LSB +38.15 μV
00001
Midscale
0V
00000
Midscale – 1 LSB −38.15 μV
3FFFF
–FSR + 1 LSB
−4.999962 V 20001
–FSR
−5 V
200002
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF −
VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
V+
V+
0 TO VREF
V-
V+
VREF TO 0
ADA4841-2 or
note 3
V-
REF1
10μF2
20Ω
2.7nF
4
20Ω
2.7nF
4
REF
IN+
VDD
VIO
SDI
AD7982
SCK
SDO
IN–
GND
CNV
100nF
100nF
2.5V
1.8V TO 5V
3-WIRE INTERFACE
1SEE REFERENCE SECTION FOR REFERENCE SELECTION.
2CREF IS USUALLY A 10μF CERAMIC CAPACITOR (X5R).
3SEE DRIVER AMPLIFIER CHOICE SECTION.
4OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
Figure 13. Typical Application Diagram with Multiple Supplies
Rev PrC | Page 11 of 23
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet AD7982.PDF ] | |
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