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PDF SC18IM700 Data sheet ( Hoja de datos )
| Número de pieza | SC18IM700 | |
| Descripción | Master I-2C - bus controller | |
| Fabricantes | NXP Semiconductors | |
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SC18IM700
Master I2C-bus controller with UART interface
Rev. 01 — 28 February 2006
Product data sheet
1. General description
The SC18IM700 is designed to serve as an interface between the standard UART port of
a microcontroller or microprocessor and the serial I2C-bus; this allows the microcontroller
or microprocessor to communicate directly with other I2C-bus devices. The SC18IM700
can operate as an I2C-bus master. The SC18IM700 controls all the I2C-bus specific
sequences, protocol, arbitration and timing. The host communicates with SC18IM700 with
ASCII messages protocol; this makes the control sequences from the host to the
SC18IM700 become very simple.
2. Features
s UART host interface
s I2C-bus controller
s Eight programmable I/O pins
s High-speed UART: baud rate up to 460.8 kbit/s
s High-speed I2C-bus: 400 kbit/s
s 16-byte TXFIFO
s 16-byte RXFIFO
s Programmable baud rate generator
s 2.3 V and 3.6 V operation
s Sleep mode (power-down)
s UART message format resembles I2C-bus transaction format
s I2C-bus master functions
s Multi-master capability
s 5 V tolerance on the input pins
s 8 N 1 UART format (8 data bits, no parity bit, 1 stop bit)
s Available in very small TSSOP16 package
3. Applications
s Enable I2C-bus master support in a system
s I2C-bus instrumentation and control
s Industrial control
s Medical equipment
s Cellular telephones
s Handheld computers
1 page  
Philips Semiconductors
SC18IM700
Master I2C-bus controller with UART interface
host sends
S CHAR.
SLAVE ADR.
+W
NUMBER
OF BYTES
DATA 0
Fig 3. Write N bytes to slave device
DATA N P CHAR.
002aac048
7.1.2 Read N byte from slave device
The host issues the read command by sending an S character followed by an I2C-bus
slave device address, and the total number of bytes to be read from the addressed
I2C-bus slave. The frame is then terminated with a P character. Once the host issues this
command, the SC18IM700 will access the I2C-bus slave device, get the correct number of
bytes from the addressed I2C-bus slave, and then return the data to the host.
Note that the second byte sent is the I2C-bus device slave address. The least significant
bit (R) of this byte must be set to 1 to indicate this is an I2C-bus write command.
host sends
S CHAR.
SLAVE ADR.
+R
NUMBER
OF BYTES
P CHAR.
18IM responds
DATA 0
DATA N
Fig 4. Read N byte from slave device
002aac049
7.1.3 Write to 18IM internal register
The host issues the internal register write command by sending a W character followed by
the register and data pair. Each register to be written must be followed by the data byte.
The frame is then terminated with a P character.
W CHAR. REGISTER 0
DATA 0
Fig 5. Write to 18IM internal register
REGISTER N
DATA N
P CHAR.
002aac050
Remark: Write and read from the internal 18IM register is processed immediately as soon
as the intended register is determined by 18IM.
SC18IM700_1
Product data sheet
Rev. 01 — 28 February 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
5 of 21
5 Page 
Philips Semiconductors
SC18IM700
Master I2C-bus controller with UART interface
9.2.2.4 Open-drain output configuration
The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resistor
tied to VDD.
An open-drain port pin has a Schmitt triggered input that also has a glitch suppression
circuit.
pin latch data
VSS
input data
Fig 16. Open-drain output configuration
GPIO pin
glitch rejection
002aab883
9.2.3 Programmable I/O pins state register (IOState)
When read, this register returns the actual state of all I/O pins. When written, each
register bit will be transferred to the corresponding I/O pin programmed as output.
Table 6:
Bit
7:0
IOState - Programmable I/O pins state register (address 0x04h) bit description
Symbol
Description
IOLevel
Set the logic level on the output pins.
Write to this register:
logic 0 = set output pin to zero
logic 1 = set output pin to one
Read this register returns states of all pins.
9.2.4 I2C-bus address register (I2CAdr)
The contents of the register represents the device’s own I2C-bus address. The most
significant bit corresponds to the first bit received from the I2C-bus after a START
condition. A logic 1 in I2CAdr corresponds to a HIGH level on the I2C-bus, and a logic 0
corresponds to a LOW level on the I2C-bus. The least significant bit is not used, but should
be programmed with a ‘0’.
I2CAdr is not needed for device operation, but should be configured so that its address
does not conflict with an I2C-bus device address used by the bus master.
9.2.5 I2C-bus clock rates (I2CClk)
This register determines the serial clock frequency. The various serial rates are shown in
Table 7. The frequency can be determined using the following formula:
bit frequency = 2-----×-----(--I--2---7C---.-C3---7-l--k2---H8-----×-+----1-I--02---C6----C---l--k---L----)-
I2CClkH determines the SCL HIGH period, and I2CClkL determines the SCL LOW period.
SC18IM700_1
Product data sheet
Rev. 01 — 28 February 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
11 of 21
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