|
|
PDF HA9P2425-5 Data sheet ( Hoja de datos )
| Número de pieza | HA9P2425-5 | |
| Descripción | 3.2s Sample and Hold Amplifiers | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de HA9P2425-5 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
|
No Preview Available !
HA-2420, HA-2425
November 1996
3.2µs Sample and Hold Amplifiers
Features
• Maximum Acquisition Time
- 10V Step to 0.1%. . . . . . . . . . . . . . . . . . . . . 4µs (Max)
- 10V Step to 0.01%. . . . . . . . . . . . . . . . . . . . 6µs (Max)
• Low Droop Rate (CH = 1000pF). . . . . . . . 5µV/ms (Typ)
• Gain Bandwidth Product . . . . . . . . . . . . . 2.5MHz (Typ)
• Low Effective Aperture Delay Time . . . . . . . 30ns (Typ)
• TTL Compatible Control Input
• ±12V to ±15V Operation
Applications
• 12-Bit Data Acquisition
• Digital to Analog Deglitcher
• Auto Zero Systems
• Peak Detector
• Gated Operational Amplifier
Ordering Information
PART NUMBER
HA1-2420-2
HA1-2425-5
HA3-2425-5
HA4P2425-5
HA9P2425-5
TEMP.
RANGE (oC)
PACKAGE
-55 to 125 14 Ld CERDIP
0 to 75 14 Ld CERDIP
0 to 75 14 Ld PDIP
0 to 75 20 Ld PLCC
0 to 75 14 Ld SOIC
PKG.
NO.
F14.3
F14.3
E14.3
N20.35
M14.15
Description
The HA-2420 and HA-2425 is a monolithic circuit consisting
of a high performance operational amplifier with its output in
series with an ultra-low leakage analog switch and JFET
input unity gain amplifier.
With an external hold capacitor connected to the switch output,
a versatile, high performance sample-and-hold or track-and-
hold circuit is formed. When the switch is closed, the device
behaves as an operational amplifier, and any of the standard op
amp feedback networks may be connected around the device
to control gain, frequency response, etc. When the switch is
opened the output will remain at its last level.
Performance as a sample-and-hold compares very favorably
with other monolithic, hybrid, modular, and discrete circuits.
Accuracy to better than 0.01% is achievable over the
temperature range. Fast acquisition is coupled with superior
droop characteristics, even at high temperatures. High slew
rate, wide bandwidth, and low acquisition time produce
excellent dynamic characteristics. The ability to operate at
gains greater than 1 frequently eliminates the need for
external scaling amplifiers.
The device may also be used as a versatile operational
amplifier with a gated output for applications such as analog
switches, peak holding circuits, etc. For more information,
please see Application Note AN517.
The MIL-STD-883 data sheet for this device is available on
request.
Pinouts
HA-2420 (CERDIP)
HA-2425 (CERDIP, PDIP, SOIC)
TOP VIEW
-IN 1
+IN 2
OFFSET ADJ. 3
OFFSET ADJ. 4
V- 5
NC 6
OUTPUT 7
14 S/H CONTROL
13 GND
12 NC
11 HOLD CAP.
10 NC
9 V+
8 NC
HA-2425
(PLCC)
TOP VIEW
3 2 1 20 19
OFFSET ADJ. 4
NC 5
OFFSET ADJ. 6
NC 7
V- 8
18 NC
17 NC
16 HOLD CAP.
15 NC
14 NC
9 10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
5-1
File Number 2856.2
1 page  
HA-2420, HA-2425
Application Information
HOLD STEP VOLTAGE (mV)
+10
INPUT
+IN
-IN
S/H
CONTROL
OUT
OUTPUT
5
-10 -5
0
-5
-10
-15
-20
+5 +10
DC INPUT VOLTAGE (V)
CH = 0.1µF
CH = 10,000pF
CH = 1000pF
-25
-30 CH = 100pF
-35
FIGURE 5. HOLD STEP vs INPUT VOLTAGE
Offset Adjustment
The offset voltage of the HA-2420 and HA-2425 may be
adjusted using a 100kΩ trim pot, as shown in Figure 8. The
recommended adjustment procedure is:
Apply 0V to the sample-and-hold input, and a square wave
to the S/H control.
Adjust the trim pot for 0V output in the hold mode.
Gain Adjustment
The linear variation in pedestal voltage with sample-and- hold
input voltage causes a -0.06% gain error (CH = 1000pF). In
some applications (D/A deglitcher, A/D converter) the gain
error can be adjusted elsewhere in the system, while in other
applications it must be adjusted at the sample-and-hold. The
two circuits shown below demonstrate how to adjust gain error
at the sample-and-hold.
The recommended procedure for adjusting gain error is:
1. Perform offset adjustment.
2. Apply the nominal input voltage that should produce a
+10V output.
3. Adjust the trim pot for +10V output in the hold mode.
4. Apply the nominal input voltage that should produce a
-10V output.
5. Measure the output hold voltage (V-10NOMINAL). Adjust
the trim pot for an output hold voltage of
(---V-----–--1----0----N-----O------M-----I--N-----A----L-----)---+-----(------1---0----V------)
2
RI RF
0.002RI
S/H CONTROL
INPUT
NOTE: GAIN ~ 1 + R--R---F-I-
FIGURE 7. NON-INVERTING CONFIGURATION
Figure 8 shows a typical unity gain circuit, with Offset Zero-
ing. All of the other normal op amp feedback configurations
may be used with the HA-2420/2425. The input amplifier
may be used as a gated amplifier by utilizing Pin 11 as the
output. This amplifier has excellent drive capabilities along
with exceptionally low switch leakage.
CONTROL
CH
V+
-+
+-
IN V-
OUT
100kΩ
OFFSET TRIM (±25mV RANGE)
FIGURE 8. BASIC SAMPLE-AND-HOLD (TOP VIEW)
The method used to reduce leakage paths on the PC board
and the device package is shown in Figure 9. This guard ring
is recommended to minimize the drift during hold mode.
The hold capacitor should have extremely high insulation
resistance and low dielectric absorption. Polystyrene (below
85oC), Teflon, or Parlene types are recommended.
For more applications, consult Intersil Application Note
AN517, or the factory applications group.
GND
CONTROL
-IN
HOLD
CAPACITOR
+IN
RF 0.002RF
INPUT RI
-IN
OUT
OUTPUT
+IN
S/H CONTROL INPUT
S/H
CONTROL
NOTE: GAIN ∼ -–--R-R----IF--
FIGURE 6. INVERTING CONFIGURATION
OUT
V+
V-
FIGURE 9. GUARD RING LAYOUT (BOTTOM VIEW)
5-5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet HA9P2425-5.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| HA9P2425-5 | 3.2s Sample and Hold Amplifiers | Intersil Corporation |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |