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GF9101 PDF даташит

Спецификация GF9101 изготовлена ​​​​«Gennum» и имеет функцию, называемую «High Performance Multirate Digital Filter».

Детали детали

Номер произв GF9101
Описание High Performance Multirate Digital Filter
Производители Gennum
логотип Gennum логотип 

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GF9101 Даташит, Описание, Даташиты
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MultiGEN GF9101 High
Performance Multirate Digital Filter
FEATURES
• highly optimized & flexible architecture for multirate
FIR filtering applications
• implements dual 12 tap filters operating at 40 MHz or
single 23 or 24 tap filter operating at 20 MHz maximum
data rate
• stores up to 108 fully-programmable 12 tap filters with
12 bit coefficients at each tap, dynamically
addressable in each clock cycle
• 3 flexible memory loading modes
• 20 bit pipeline for cascading up to 3 devices
• 20 bit output accumulator
• filter output negate and zero controls
• supports both symmetrical and asymmetrical FIR
filters
• 40 MHz maximum computation and input/output data
rates
DESCRIPTION
DATA SHEET
The GF9101 is a high performance multirate digital filter
which can be programmed to implement a wide range of
signal processing functions using both symmetrical and
asymmetrical filter structures. It is composed of a 12-tap
FIR filter with internal RAM to hold up to 108 individual
filters. An externally controlled address bus selects one of
the 108 filters in each clock cycle. Pipelined architecture
allows cascading of up to three devices with no additional
hardware.
Two 10-bit input shift registers are provided for multiplexed
filtering applications. The 12-bit coefficients can be
programmed in serial, high speed parallel or
microprocessor modes. In the high speed parallel mode,
any one of the 108 filters can be reprogrammed in 18 clock
cycles.
ORDERING INFORMATION
APPLICATIONS
Video rate conversion; High performance FIR filters;
Adaptive digital filters; Video encoding; Digital modulation
PART NUMBER
GF9101 - CMQ
PACKAGE
160 pin Metal Quad
TEMPERATURE
0° to 70°C
+10
DATA–A–IN
ENA
+10
DATA–B–OUT
ENB
R
R
SEL–A/B
ENC
R
R
COEF–ADDR R
1
0
TAP TAP
CELL CELL
12
7
TAP
CELL
11
7
+10
DATA–A–OUT
+10
TAP DATA–B–IN
CELL
12
ZERO
NEGATE
R
R
Σ
±14.11
4R
±13.6 TRUNCATED
DELAY
1,3,4,5
2
R DELAY SEL
±13.6
CONFIGURATION
REGISTER
DATA B SEL
PIPELINE–IN
±13.6
CARRY
IN
±13.6
R
±13.6
0+
1 ±13.6
R
±13.6
PIPELINE–OUT
Revision Date: July 1999
FB–SEL R
BLOCK DIAGRAM
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
Document No. 520 - 64 - 7









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GF9101 Даташит, Описание, Даташиты
I/O DESCRIPTION
SYMBOL
VDD
GND
CLK_IN
DATA_A_IN (9-0)
DATA_B_IN (9-0)
ENA
ENB
ENC
SEL_A/B
COEF_DATA (7-0)
COEF_ADDR (9-0)
COEF_WR
LOAD_EN
NEGATE
ZERO
FB_SEL
PIN NO.
1, 10, 20, 29, 40, 41,
59, 69, 80, 81, 90, 99,
109, 120, 121, 129,
140, 150, 160
3, 6, 8, 19, 33, 36, 39,
46, 49, 60, 73, 76, 79,
83, 86, 88, 100, 113,
116, 119, 122, 125,
139, 153, 155, 159
138
127, 128, 130-137
141-149, 151
23
24
25
22
96-98, 101-105
78, 77, 75, 74, 72, 47,
45-42
17
18
126
123
124
TYPE
DESCRIPTION
+5 V power supply pins. 0.1µF capacitors between the VCC and GND pins
are recommended.
Device ground.
I System clock. All inputs except for CONFIGURE, and all internal registers are
clocked on the rising edge of CLK_IN.
I Input data to registers A0 - A11. 9 bit signed or 10 bit unsigned data.
I Input data to registers B11 - B0. 9 bit signed or 10 bit unsigned data.
I Shift enable for A0 - A11. Enables shifting of A registers when high.
I Shift enable for B0 - B11. Enables shifting of B registers when high.
I Enable for C0-C11. Enables C registers when high. The C registers transfer
data from either the A or B registers depending on the state of SEL_A/B.
I Selects A or B registers. Selects registers A when high or registers B when
low to be transferred to the C registers.
I Data bus for coefficients and configuration register:
a) Parallel and microprocessor loading modes : COEF_DATA (7-0) is used to
load 8 bit data into internal RAM.
b) Serial Loading mode: COEF_DATA (7) is used to serially load the internal
RAM.
c) Configuration mode: COEF_DATA (6-0) are inputs to the CONFIGURATION
register.
I Address bus for internal RAM (address 0 > 107):
a) Run mode: COEF_ADDR (6-0) selects one of the 108 sets of 12 coefficients
in the internal RAM.
b) Parallel and micro-processor loading modes: Selects the internal RAM
address for the 8-bit data loading COEF_DATA (7-0).
I Enable for COEF_DATA (7-0). LOAD_EN must be enabled for COEF_WR to
work:
a) Parallel and micro-processor loading modes : Enables COEF_DATA (7-0)
registers or loading 8 bit data in internal RAM.
b) Serial Loading mode: On a high to low transition, a one bit data gets
clocked in to the internal RAM through COEF_DATA bit 7.
I Used during loading mode. This signal selects a particular GF9101 device
when 2 or more share the same bus for loading. The particular GF9101
device is selected when set low. LOAD_EN must be enabled for COEF_WR.
For a single GF9101 using the serial loading, this pin can be set low.
I This signal negates the filter sum before it enters the pipelined output section
when high.
I Zeros filter sum before it enters the pipelined output section when low.
I Feedback select. Selects data in PIPELINE_IN when low or filter sum in
PIPELINE_OUT when high to the input of the output accumulator.
520 - 64 - 7
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GF9101 Даташит, Описание, Даташиты
I/O DESCRIPTION
SYMBOL
PIN NO.
TYPE
DESCRIPTION
CONFIGURE
21 I GF9101 reset/configure. Resets the GF9101 when high for at least one clock
period. Loads COEF_DATA (6-0) into the CONFIGURATION register on a high
to low transition. This bit is set low in run mode. When CONFIGURE is high,
the GF9101 is reset but the values in the internal RAM and registers in the run
mode sections are not altered. This means that the GF9101 may be
reconfigured after the internal RAM has been loaded.
PIPELINE_IN (19-0)
38,37, 35, 34, 32-30,
28-26, 15-11, 9, 7, 5,
4, 2
I Pipeline input. Input to the output accumulator when FB_SEL is low.
DATA_A_OUT (9-0)
71, 70, 68-61
O Output data from register A11.
DATA_B_OUT (9-0)
58-50, 48
O Output data from register B0.
PIPELINE_OUT (19- 82, 84, 85, 87, 89, 91- O Pipeline output. Output of the accumulator or PIPELINE_IN depending on
0)
95, 106-108, 110-
FB_SEL.
112, 114, 115, 117,
118
S_LOAD_CMP
16 O Serial loading complete.
a) Serial loading mode: When high, indicates that all the internal RAM has
been loaded.
SCAN_IN, SCAN_EN
157, 156
Set low.
TEST
158 Set high.
POUT, SCANOUT
152, 154
No Connect.
Note: All unused inputs of the GF9101 should be connected to GND
GF9101 OPERATION
The GF9101 has two operating modes: the load mode and
the run mode. In the load mode, the coefficients for the
filters are written to the internal RAM. In the run mode, the
GF9101 is used to filter signals.
Before the GF9101 can filter signals, two steps must be
performed:
1. CONFIGURATION - is accomplished by writing one 7 bit
word into the CONFIGURATION REGISTER. This register
holds static operating parameters that affect both the
load mode and the run mode.
2. MEMORY LOADING - is done after configuration. The
internal RAM must be loaded with at least one of the 108
filter coefficient sets before signals can be processed.
CONFIGURATION
The GF9101 is reset by holding CONFIGURE high for at
least one clock cycle. Configuration occurs upon a high to
low transition on the CONFIGURE pin. This transition
registers COEF_DATA (6-0) into the CONFIGURATION
REGISTER. Table 1 shows the meaning of each bit in the
CONFIGURATION REGISTER.
When CONFIGURE is high, the GF9101 is reset but the
values in the internal RAM and registers in the run mode
sections are not altered. This means that the GF9101 may
be reconfigured after the internal RAM has been loaded.
MEMORY LOADING
The GF9101 contains 12 tap cells with 108 12-bit memory
locations for each tap. When loading the memory, the tap
cells must be viewed as 6 memory banks with 108 24-bit
memory locations in each bank. Each memory bank is
assigned to a pair of tap cells as shown in Table 2.
During configuration, either the parallel, microprocessor, or
serial loading is selected. When in the load mode, the
memory outputs are undefined. Please refer to the GF9101
block diagram and notice that, even though the memory
outputs are undefined, several valid outputs may be in the
processing section below the multipliers and can exit the
GF9101 correctly. This would be useful for adaptive filtering
where the tap memories can be changed while the GF9101
outputs are still valid. During power up, the internal RAM of
the GF9101 is in a random state, and is not intialized to
zero.
3
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