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PDF GF9105A Data sheet ( Hoja de datos )
| Número de pieza | GF9105A | |
| Descripción | Component Digital Transcoder | |
| Fabricantes | Gennum | |
| Logotipo |  |
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MultiGENTM GF9105A
Component Digital Transcoder
FEATURES
• drop in replacement for the GF9105 with lower power
and increased functionality
• new mode for HVF output
• new mode for using low frequency clocks with non-
multiplexed I/O data
• optimized HOST IF control signals for ensured shared
bus compatibility
• multiple format conversions from one device
4:2:2:4 <-> 4:4:4:4
4:2:2:4 <-> R/G/B/KEY
4:2:2:4 <-> Y/U/V/KEY
Y/U/V/KEY <-> R/G/B/KEY
4:4:4:4 <-> R/G/B/KEY
4:4:4:4 <-> Y/U/V/KEY
• ITU-R-601 compliant interpolation/decimation filters
• supports both single link 4:4:4:4 (SMPTE RP174) and
dual link 4:4:4:4 (SMPTE RP175) compliant I/O
• transparent conversions between Y/U/V and R/G/B
color spaces.
• fully programmable 3X3 Color Space Converter (CSC)
• 13 bit Color Space Converter coefficients
• 13 bit KEY Channel scaling coefficient
• multiplexed and non-multiplexed I/O data
• bi-directional I/O data ports with tri-stating
• parallel HOST IF for reading and writing multiplier
coefficients and device configuration words
• single +5V power supply.
ORDERING INFORMATION
PART NUMBER
GF9105ACQQ
PACKAGE
160 Pin MQFP
DATA SHEET
DEVICE OVERVIEW
The GF9105A is a drop in replacement for the GF9105 with
lower power and increased functionality. This increased
functionality gives the user the option of having HVF output
signals and the option of using a low frequency clock when
operating with non-multiplexed input and output data. The
GF9105A is a flexible VDSP engine capable of performing a
variety of format conversions. The flexible architecture of
the GF9105A also allows the user to perform a wide range
of DSP functions that require a general 3X3 multiplier
structure and/or high performance 1:2 interpolation and 2:1
decimation filters. Device configuration is selected by
writing configuration words through an asynchronous
parallel interface (HOST IF).
The GF9105A accepts either multiplexed or non-
multiplexed input data and may produce either multiplexed
or non-multiplexed output data. External H, V and F inputs
allow for the insertion of TRS words into multiplexed output
data streams.
All interpolation and decimation filtering required for ITU-R-
601 compliant 4:2:2:4 <-> 4:4:4:4 sample rate conversions
has been integrated into the GF9105A. In addition, all input
and output offset adjustments required for transparent
conversions between the Y/U/V and R/G/B color spaces
have been included within the GF9105A.
The color space converter within the GF9105A has 13 bit
multiplier coefficients, has 13 bit output resolution,
maintains full precision throughout the 3X3 calculation and
has a true unity gain by-pass mode. Sufficient resolution is
maintained within the color space converter to ensure that
truly transparent Y/U/V <-> R/G/B conversions may be
achieved. A user programmable output clipper allows the
GF9105A to output a variety of word lengths to meet
specific system requirements.
The GF9105A is packaged in a 160 pin MQFP package,
operates from a single +5V supply.
Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R, OR Y/G
XX OR CB/B
13
13
XX OR CR/R
13
11
KEY, CB/B, CR/R OR KEY
Y/G Y/G
DEMUX
4:4:4:4
OR
4:2:2:4
CB/B
CR/R
H_BLANK
AND
INPUT
OFFSET
ADJUST
CB/B
CR/R
KEY KEY
Y/G
INT
CB/B
INT
CR/R
KEY
3X3
MATRIX
MULTIPLIER
KEY SCALER
Y/G
CB/B
CR/R
KEY
Y/G
DEC
CB/B
DEC
CR/R
Y/G
OUTPUT
OFFSET CB/B
ADJUST
CR/R
KEY KEY
Y/G
OUTPUT
CLIP
CB/B
CR/R
OUTPUT
MULTIPLEXER
KEY
13 Y/G, CB/B, CR/R, KEY OR
Y/G, CB/B, CR/R, OR Y/G
13
CB/B OR XX
13
CR/R OR XX
11
KEY OR KEY, CB/B, CR/R
GENERAL FUNCTIONALITY OF GF9105A CORE
Revision Date: March 2000
Document No. 521 - 88 - 03
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
1 page  
OUTPUT/INPUT = 0
P112..0
P212..0
P312..0
P410..0
13
13
13
11
13
C1
13
C2
13
C3
11
C4
P512..0
P612..0
P712..0
P810..0
13
13
13
11
13
C5
13
C6
13 C7
11
C8
BI-DIRECTIONAL
DATA PORTS
GF9105A SIGNAL
PROCESSING CORE
Fig. 4a Functional Block Diagram of GF9105A
(OUTPUT/INPUT = 0, HVF_OUT = 0)
OUTPUT/INPUT = 0
P112/HOUT
P111..0
P212/VOUT
P211..0
P312/FOUT
P311..0
P410..0
12
12
12
11
}12 C1
}12 C2
}12 C3
}11
C4
P5
12
P5
11..0
P6
12
P6
11..0
P7
12
P7
11..0
P8
10..0
12
12
12
11
BI-DIRECTIONAL
DATA PORTS
}12 C5
}12 C6
}12 C7
}11
C8
GF9105A SIGNAL
PROCESSING CORE
Fig. 4c Functional Block Diagram of GF9105A
(OUTPUT/INPUT = 0, HVF_OUT = 1)
OUTPUT/INPUT = 1
P1
12..0
P2
12..0
P3
12..0
P4
10..0
13
13
13
11
13
C1
13
C2
13
C3
11
C4
P5
12..0
P6
12..0
P7
12..0
P8
10..0
13
13
13
11
13
C5
13
C6
13
C7
11
C8
BI-DIRECTIONAL
DATA PORTS
GF9105A SIGNAL
PROCESSING CORE
Fig. 4b Functional Block Diagram of GF9105A
(OUTPUT/INPUT = 1, HVF_OUT = 0)
OUTPUT/INPUT = 1
P112/HOUT
P111..0
P212/VOUT
P211..0
P312/FOUT
P311..0
P410..0
12
12
12
11
}12 C1
}12 C2
}12 C3
}11
C4
P5
12
P5
11..0
P6
12
P6
11..0
P7
12
P7
11..0
P8
10..0
12
12
12
11
BI-DIRECTIONAL
DATA PORTS
}12 C5
}12 C6
}12 C7
}11
C8
GF9105A SIGNAL
PROCESSING CORE
Fig. 4d Functional Block Diagram of GF9105A
(OUTPUT/INPUT = 1, HVF_OUT = 1)
5 521 - 88 - 03
5 Page 
OUTPUT/INPUT = 0, HVF_OUT = 1
13 BIT PHYSICAL INTERFACE
DATA PORT REFERENCE
Input Port: P112..0 to P312..0
Embedded 10 bit signal
b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
H, V, or F
output
0
0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Input Port: P410..0
Embedded 10 bit signal
NA NA 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Input Port: P112..0 to P312..0
Embedded 8 bit signal
H, V, or F
output
0
0 b7 b6 b5 b4 b3 b2 b1 b0 0
0
Input Port: P410..0
Embedded 8 bit signal
NA
NA 0 b7 b6 b5 b4 b3 b2 b1 b0 0
0
OUTPUT/INPUT = 1, HVF_OUT = 0
DATA PORT REFERENCE
Input Port: P512..0 to P712..0
Embedded 10 bit signal
Input Port: P810..0
Embedded 10 bit signal
Input Port: P512..0 to P712..0
Embedded 8 bit signal
Input Port: P810..0
Embedded 8 bit signal
13 BIT PHYSICAL INTERFACE
b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
NA NA 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0
NA
NA 0 b7 b6 b5 b4 b3 b2 b1 b0 0
0
OUTPUT/INPUT = 1, HVF_OUT = 1
DATA PORT REFERENCE
Input Port: P512..0 to P712..0
Embedded 10 bit signal
Input Port: P810..0
Embedded 10 bit signal
Input Port: P512..0 to P712..0
Embedded 8 bit signal
Input Port: P810..0
Embedded 8 bit signal
13 BIT PHYSICAL INTERFACE
b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
NA NA 0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0
NA
NA 0 b7 b6 b5 b4 b3 b2 b1 b0 0
0
(refer to Figures 4a and 4c). While OUTPUT/INPUT=1 Processing Core port C1 corresponds to device data port P5 (Refer to
Figures 4b and 4d).
The KEY:2:2 or KEY:XX:XX data enters the GF9105A Processing Core from Processing Core input port C4. While OUTPUT/
INPUT=0, Processing Core port C4 corresponds to device data port P4 (Refer to Figures 4a and 4c). While OUTPUT/
INPUT=1, Processing Core port C4 corresponds to device data port P8 (Refer to Figures 4b and 4d).
When MUXED_IN is set high, input data is assumed to be 4:2:2:4 or 4:4:4:4 data in a non-multiplexed format as shown in
Figure 7c. Since the incoming data is already non-multiplexed, the input data is passed on to the next processing section
unmodified. In this mode of operation, input data is presented to all four Processing Core input ports. While OUTPUT/
INPUT=0, Processing Core ports C1-C4 correspond to device data ports P1-P4 (Refer to Figures 4a and 4c). While OUTPUT/
INPUT=1 Processing Core ports C1-C4 correspond to device data ports P5-P8 (Refer to Figure 4b and 4d).
11 521 - 88 - 03
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet GF9105A.PDF ] | |
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