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PDF ZL50011 Data sheet ( Hoja de datos )
| Número de pieza | ZL50011 | |
| Descripción | Flexible 512 Channel DX | |
| Fabricantes | Zarlink Semiconductor | |
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ZL50011
Flexible 512 Channel DX with on-chip
DPLL
Data Sheet
Features
July 2005
• 512 channel x 512 channel non-blocking switch at
2.048 Mbps, 4.096 Mbps or 8.192 Mbps
operation
• Rate conversion between the ST-BUS inputs and
ST-BUS outputs
• Integrated Digital Phase-Locked Loop (DPLL)
meets Telcordia GR-1244-CORE Stratum 4
specifications
• DPLL provides reference monitor, jitter
attenuation and free run functions
• Per-stream ST-BUS input with data rate selection
of 2.048 Mbps, 4.096 Mbps or 8.192 Mbps
• Per-stream ST-BUS output with data rate
selection of 2.048 Mbps, 4.096 Mbps or
8.192 Mbps; the output data rate can be different
than the input data rate
• Per-stream high impedance control output for
every ST-BUS output with fractional bit
advancement
• Per-stream input channel and input bit delay
programming with fractional bit delay
Ordering Information
ZL50011/QCC 160 Pin LQFP
ZL50011/GDC 144 Ball LBGA
• Per-stream output channel and output bit delay
programming with fractional bit advancement
• Multiple frame pulse outputs and reference clock
outputs
• Per-channel constant throughput delay
• Per-channel high impedance output control
• Per-channel message mode
• Per-channel Pseudo Random Bit Sequence
(PRBS) pattern generation and bit error detection
• Control interface compatible to Motorola non-
multiplexed CPUs
• Connection memory block programming capability
• IEEE-1149.1 (JTAG) test port
• 3.3 V I/O with 5 V tolerant input
VDD
VSS
RESET
ODE
STi0-15
FPi
CKi
REF
S/P Converter
Input Timing
Data Memory
Connection Memory
DPLL
OSC
APLL
Microprocessor
Interface
and
Internal
Registers
P/S Converter
Output HiZ Control
Output Timing
Test Port
STo0-15
STOHZ0-15
FPo0
CKo0
FPo1
CKo1
FPo2
CKo2
IC0 - 4
CLKBYPS
ICONN1
Figure 1 - ZL50011 Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL50011
Data Sheet
List of Figures
Figure 1 - ZL50011 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - 24 mm x 24 mm LQFP (JEDEC MS-026) Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3 - 13 mm x 13 mm 144 Ball LBGA Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4 - Input Timing when (CKIN2 to CKIN0 bits = 010) in the Control Register . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5 - Input Timing when (CKIN2 to CKIN0 bits = 001) in the Control Register . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6 - Input Timing when (CKIN2 to CKIN0 bits = 000) in the Control Register . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7 - ST-BUS Input Timing for Various Input Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8 - FPo0 and CKo0 Output Timing when the CKFP0 Bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9 - FPo0 and CKo0 Output Timing when the CKFP0 Bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10 - FPo1 and CKo1 Output Timing when the CKFP1 Bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11 - FPo1 and CKo1 Output Timing when the CKFP1 Bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12 - FPo2 and CKo2 Output Timing when the CKFP2 Bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13 - FPo2 and CKo2 Output Timing when the CKFP2 Bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14 - ST-BUS Output Timing for Various Output Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15 - Input Channel Delay Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16 - Input Bit Delay Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17 - Output Channel Delay Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18 - Output Bit Delay Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19 - Fractional Output Bit Advancement Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20 - Example: External High Impedance Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 21 - Data Throughput Delay when Input and Output Channel Delay are Disabled for Input Ch0 Switched
to Output Ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 22 - Data Throughput Delay when Input Channel Delay is Enabled and Output Channel Delay is Disabled
for Input Ch0 Switched to Output Ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 23 - Data Throughput Delay when Input Channel Delay is Disabled and Output Channel Delay is Enabled
for Input Ch0 Switch to Output Ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 24 - Data Throughput Delay when Input and Output Channel Delay are Enabled for Input Ch0 Switched to
Output Ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 25 - DPLL Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 26 - Skew Control Circuit Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 27 - Block Diagram of the PLL Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 28 - DPLL Jitter Transfer Function Diagram - Wide Range of Frequencies . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 29 - Detailed DPLL Jitter Transfer Function Diagram (Wander Transfer Diagram) . . . . . . . . . . . . . . . . . . 39
Figure 30 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 31 - External Clock Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 32 - Frame Pulse Input and Clock Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 33 - Frame Boundary Timing with Input Clock (Cycle-to-Cycle) Variation . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 34 - Frame Boundary Timing with Input Frame Pulse (Cycle-to-Cycle) Variation. . . . . . . . . . . . . . . . . . . . 69
Figure 35 - XTALi Input Timing Diagram when Clock Oscillator is Connected . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 36 - Reference Input Timing Diagram when the Input Frequency = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 37 - Reference Input Timing Diagram when the Input Frequency = 2.048 MHz. . . . . . . . . . . . . . . . . . . . . 71
Figure 38 - Reference Input Timing Diagram when the Input Frequency = 1.544 Hz . . . . . . . . . . . . . . . . . . . . . . 71
Figure 39 - Input and Output Frame Boundary Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 40 - FPo0 and CKo0 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 41 - FPo1 and CKo1 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 42 - FPo2 and CKo2 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 43 - ST-BUS Inputs (STi0 - 15) Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 44 - ST-BUS Outputs (STo0 - 15) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 45 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
5
Zarlink Semiconductor Inc.
5 Page 
ZL50011
Data Sheet
Pin Description
LQFP Pin
Number
LBGA Ball
Number
10, 23, 33,
43, 48, 58,
68, 78, 92,
102, 113,
127, 136,
146, 156
D5, D6, D7
E9
F4, F9
G4
H4
J6, J7, J8
9, 18, 21,
32, 38, 47,
57, 67, 77,
91, 101,
112, 126,
135, 145,
155
D4, D9
E5, E6, E7, E8
F5, F6, F7, F8
G5, G6, G7,
G8
H5, H6, H7, H8
J4
3 B12
4 A12
5 B11
6 A11
7 B10
8 A10
Name
VDD
Vss (GND)
TMS
TCK
TRST
TDi
FPi
CKi
Description
Power Supply for the device: +3.3 V
Ground.
Test Mode Select (3.3 V Tolerant Input with internal
pull-up): JTAG signal that controls the state transitions of the
TAP controller. This pin is pulled high by an internal pull-up
resistor when it is not driven.
Test Clock (5 V Tolerant Input): Provides the clock to the
JTAG test logic.
Test Reset (3.3 V Tolerant Input with internal pull-up):
Asynchronously initializes the JTAG TAP controller by putting it
in the Test-Logic-Reset state. This pin should be pulsed low
during power-up to ensure that the device is in the normal
functional mode. When JTAG is not being used, this pin should
be pulled low during normal operation.
Test Serial Data In (3.3 V Tolerant Input with internal
pull-up): JTAG serial test instructions and data are shifted in
on this pin. This pin is pulled high by an internal pull-up resistor
when it is not driven.
ST-BUS Frame Pulse Input (5 V Tolerant Input): This pin
accepts the frame pulse which stays low for 61 ns, 122 ns or
244 ns at the frame boundary. The frame pulse associating
with the highest input data rate has to be applied to this pin.
The frame pulse frequency is 8 kHz. The device also accepts
positive frame pulse if the FPINP bit is high in the Internal
Mode Selection register.
ST-BUS Clock Input (5 V Tolerant Input): This pin accepts a
4.096 MHz, 8.192 MHz or 16.384 MHz clock. The input clock
frequency has to be equal to or greater than twice of the
highest input data rate. The clock falling edge defines the input
frame boundary. The device also allows the clock rising edge to
define the frame boundary by programming the CKINP bit in
the Internal Mode Selection register.
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet ZL50011.PDF ] | |
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