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ZL50019 PDF даташит

Спецификация ZL50019 изготовлена ​​​​«Zarlink Semiconductor» и имеет функцию, называемую «Enhanced 2 K Digital Switch».

Детали детали

Номер произв ZL50019
Описание Enhanced 2 K Digital Switch
Производители Zarlink Semiconductor
логотип Zarlink Semiconductor логотип 

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ZL50019 Даташит, Описание, Даташиты
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Features
• 2048 channel x 2048 channel non-blocking digital
Time Division Multiplex (TDM) switch at 8.192
and 16.384 Mbps or using a combination of ports
running at 2.048, 4.096, 8.192 and 16.384 Mbps
• 32 serial TDM input, 32 serial TDM output
streams
• Integrated Digital Phase-Locked Loop (DPLL)
exceeds Telcordia GR-1244-CORE Stratum 4E
specifications
• Output clocks have less than 1 ns of jitter (except
for the 1.544 MHz output)
• DPLL provides holdover, freerun and jitter
attenuation features with four independent
reference source inputs
• Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
ZL50019
Enhanced 2 K Digital Switch with
Stratum 4E DPLL
Data Sheet
October 2004
Ordering Information
ZL50019GAC 256-ball PBGA
ZL50019QCC 256-lead LQFP
-40°C to +85°C
• Output streams can be configured as bi-
directional for connection to backplanes
• Per-stream input and output data rate conversion
selection at 2.048, 4.096, 8.192 or 16.384 Mbps.
Input and output data rates can differ
• Per-stream high impedance control outputs
(STOHZ) for 16 output streams
• Per-stream input bit delay with flexible sampling
point selection
STi[31:0]
FPi
CKi
MODE_4M0
MODE_4M1
REF0
REF1
REF2
REF3
REF_FAIL0
REF_FAIL1
REF_FAIL2
REF_FAIL3
OSC_EN
VDD_CORE
VDD_IO
VDD_COREA VDD_IOA
VSS
RESET
ODE
S/P Converter
Data Memory
P/S Converter
Input Timing
DPLL
Connection Memory
Output HiZ
Control
Output Timing
OSC
Internal Registers &
Microprocessor Interface
Test Port
STio[31:0]
STOHZ[15:0]
FPo[3:0]
CKo[5:0]
FPo_OFF[2:0]
Figure 1 - ZL50019 Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004, Zarlink Semiconductor Inc. All Rights Reserved.









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ZL50019 Даташит, Описание, Даташиты
ZL50019
Data Sheet
• Per-stream output bit and fractional bit advancement
• Per-channel ITU-T G.711 PCM A-Law/µ-Law Translation
• Four frame pulse and six reference clock outputs
• Three programmable delayed frame pulse outputs
• Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
• Input frame pulses: 61 ns, 122 ns, 244 ns
• Per-channel constant or variable throughput delay for frame integrity and low latency applications
• Per Stream (32) Bit Error Rate Test circuits complying to ITU-O.151
• Per-channel high impedance output control
• Per-channel message mode
• Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses
• Connection memory block programming
• Supports ST-BUS and GCI-Bus standards for input and output timing
• IEEE-1149.1 (JTAG) test port
• 3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage
Applications
• PBX and IP-PBX
• Small and medium digital switching platforms
• Remote access servers and concentrators
• Wireless base stations and controllers
• Multi service access platforms
• Digital Loop Carriers
• Computer Telephony Integration
2
Zarlink Semiconductor Inc.









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ZL50019 Даташит, Описание, Даташиты
ZL50019
Data Sheet
Description
The ZL50019 is a maximum 2,048 x 2,048 channel non-blocking digital Time Division Multiplex (TDM) switch. It has
thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64 kbps and
Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be
independently programmed to operate at any of the following data rates: 2.048, 4.096, 8.192 or 16.384 Mbps. The
ZL50019 provides up to sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external
tristate drivers for the first sixteen output streams (STio0 - 15). The output streams can be configured to operate in
bi-directional mode, in which case STi0 - 31 will be ignored.
The device contains two types of internal memory - data memory and connection memory. There are four modes of
operation - Connection Mode, Message Mode, BER mode and high impedance mode. In Connection Mode, the
contents of the connection memory define, for each output stream and channel, the source stream and channel
(the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for
the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be
broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and
status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with
a pseudorandom bit sequence (PRBS) from one of 32 PRBS generators that generates a 215-1 pattern. On the
input side channels can be routed to one of 32 bit error detectors. In high impedance mode the selected output
channel can be put into a high impedance state.
When the device is operating as a timing master, the internal digital PLL is in use. In this mode, an external
20.000 MHz crystal is required for the on-chip crystal oscillator. The DPLL is phase-locked to one of four input
reference signals (which can be 8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
provided on REF0 - 3). The on-chip DPLL operates in normal, holdover or freerun mode and offers jitter
attenuation. The jitter attenuation function exceeds the Stratum 4E specification.
The configurable non-multiplexed microprocessor port allows users to program various device operating modes
and switching configurations. Users can employ the microprocessor port to perform register read/write, connection
memory read/write and data memory read operations. The port is configurable to interface with either Motorola or
Intel-type microprocessors.
The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
3
Zarlink Semiconductor Inc.










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