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ZL50062 PDF даташит

Спецификация ZL50062 изготовлена ​​​​«Zarlink Semiconductor» и имеет функцию, называемую «(ZL50062 / ZL50064) 16K-Channel Digital Switch».

Детали детали

Номер произв ZL50062
Описание (ZL50062 / ZL50064) 16K-Channel Digital Switch
Производители Zarlink Semiconductor
логотип Zarlink Semiconductor логотип 

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ZL50062 Даташит, Описание, Даташиты
www.DataSheet4U.com
ZL50062/4
16K-Channel Digital Switch with High Jitter
Tolerance, Single Rate (2, 4, 8,
or 16Mbps), and 64 Inputs and 64 Outputs
Data Sheet
Features
• 16,384-channel x 16,384-channel non-blocking
unidirectional switching.The Backplane and Local
inputs and outputs can be combined to form a
non-blocking switching matrix with 64 input
streams and 64 output streams
• 8,192-channel x 8,192-channel non-blocking
Backplane input to Local output stream switch
• 8,192-channel x 8,192-channel non-blocking
Local input to Backplane output stream switch
• 8,192-channel x 8,192-channel non-blocking
Backplane input to Backplane output switch
• 8,192-channel x 8,192-channel non-blocking
Local input to Local output stream switch
• Backplane port accepts 32 input and 32 output
ST-BUS streams with fixed data rates of
2.048Mbps, 4.096Mbps, 8.192Mbps or
16.384Mbps
• Local port accepts 32 input and 32 output ST-
BUS streams with fixed data rates of 2.048Mbps,
4.096Mbps, 8.192Mbps or 16.384Mbps
• Exceptional input clock jitter tolerance (17ns)
November 2003
Ordering Information
ZL50062GAC 256-Ball PBGA
ZL50064QCC 256-Pin LQFP
-40°C to +85°C
• Per-stream bit delay for Local and Backplane
input streams
• Per-stream advancement for Local and Backplane
output streams
• Constant 2-frame throughput delay for frame
integrity
• Per-channel high impedance output control for
Local and Backplane streams
• Per-channel driven-high output control for Local
and Backplane streams
• Per-channel message mode for Local and
Backplane output streams
• Connection memory block programming for fast
device initialization
VDD_IO VDD_CORE
VSS (GND)
RESET
ODE
BSTi0-31
Backplane Data Memories
(8,192 channels)
Local
Interface
LSTi0-31
BSTo0-31
Backplane
Interface
Backplane
Connection Memory
(8,192 locations)
Local
Connection Memory
(8,192 locations)
Local
Interface
LSTo0-31
BORS
FP8i
C8i
Input
Timing Unit
PLL
Local Data Memories
(8,192 channels)
Microprocessor Interface
and Internal Registers
Output
Timing
Unit
Test Port
LORS
FP8o
FP16o
C8o
C16o
VDD_PLL
DS CS R/W A14-0 DTA D15-0 TMS TDi TDo TCK TRST
Figure 1 - ZL50062/4 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.









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ZL50062 Даташит, Описание, Даташиты
ZL50062/4
• Automatic selection between ST-BUS and GCI-Bus operation
• Non-multiplexed Motorola microprocessor interface
• Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard
• Memory Built-In-Self-Test (BIST), controlled via microprocessor register
• 1.8V core supply voltage
• 3.3V I/O supply voltage
• 5V tolerant inputs, outputs and I/Os
Applications
• Central Office Switches (Class 5)
• Media Gateways
• Class-independent switches
• Access Concentrators
• Scalable TDM-Based Architectures
• Digital Loop Carriers
Data Sheet
2
Zarlink Semiconductor Inc.









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ZL50062 Даташит, Описание, Даташиты
ZL50062/4
Data Sheet
Device Overview
The ZL50062 and ZL50064 are two different packages of the same device. They have the same functionality
except that ZL50064 does not have 16.384MHz output clock and frame pulse (C16o and FP16o) due to package
differences. The ZL50062/4 has two data ports, the Backplane and the Local port. The device can operate at four
different data rates, 2.048Mbps, 4.096Mbps, 8.192Mbps or 16.384Mbps. All 64 input and 64 output streams must
operate at the same data rate.
The ZL50062/4 contains two data memory blocks (Backplane and Local) to provide the following switching path
configurations:
• Input-to-Output Unidirectional, supporting 16K x 16K switching
• Backplane-to-Local Bi-directional, supporting 8K x 8K data switching,
• Local-to-Backplane Bi-directional, supporting 8K x 8K data switching,
• Backplane-to-Backplane Bi-directional, supporting 8K x 8K data switching.
• Local-to-Local Bi-directional, supporting 8K x 8K data switching.
The device contains two connection memory blocks, one for the Backplane output and one for the Local output.
Data to be output on the serial streams may come from either of the data memories (Connection Mode) or directly
from the connection memory contents (Message Mode).
In Connection Mode, the contents of the connection memory define, for each output stream and channel, the
source stream and channel (stored in data memory) to be switched.
In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output
streams on a per channel basis. This feature is useful for transferring control and status information to external
circuits or other ST-BUS devices.
The device uses a master frame pulse (FP8i) and master clock (C8i) to define the input frame boundary and timing
for both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCI-
Bus style frame pulse is being used. There is a two-frame delay from the time RESET is de-asserted to the
establishment of full switch functionality. During this period, the input frame pulse format is determined before
switching begins.
The device provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the outputs of
the Backplane and Local ports.
A non-multiplexed Motorola microprocessor port allows programming of the various device operation modes and
switching configurations. The microprocessor port provides access for Register read/write, Connection Memory
read/write and Data Memory read-only operations. The port has a 15-bit address bus, 16-bit data bus and 4 control
signals. The microprocessor may monitor channel data in the Backplane and Local data memories.
The mandatory requirements of the IEEE-1149.1 (JTAG) standard are fully supported via a dedicated test port.
The ZL50062 and ZL50064 are each available in one package:
• ZL50062: a 17mm x 17mm body, 1mm ball-pitch, 256-PBGA.
• ZL50064: a 28mm x 28mm body, 0.40mm pin-pitch, 256-LQFP.
3
Zarlink Semiconductor Inc.










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