DataSheet26.com

NB4N527S PDF даташит

Спецификация NB4N527S изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «Dual AnyLevel to LVDS Receiver/Driver/Buffer/Translator».

Детали детали

Номер произв NB4N527S
Описание Dual AnyLevel to LVDS Receiver/Driver/Buffer/Translator
Производители ON Semiconductor
логотип ON Semiconductor логотип 

10 Pages
scroll

No Preview Available !

NB4N527S Даташит, Описание, Даташиты
www.DataSheet4U.com
NB4N527S
3.3V, 2.5Gb/s Dual
AnyLevelto LVDS
Receiver/Driver/Buffer/
Translator with Internal
Input Termination
NB4N527S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevelTM input signal (LVPECL, CML,
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the
distance, noise immunity of the system design, and transmission line
media, this device will receive, drive or translate data or clock signals
up to 2.5 Gb/s or 1.5 GHz, respectively.
The NB4N527S has a wide input common mode range of
GND + 50 mV to VCC − 50 mV combined with two 50 W internal
termination resistors is ideal for translating differential or
single−ended data or clock signals to 350 mV typical LVDS output
levels without use of any additional external components (Figure 6).
The device is offered in a small 3 mm x 3 mm QFN−16 package.
NB4N527S is targeted for data, wireless and telecom applications as
well as high speed logic interface where jitter and package size are
main requirements. Application notes, models, and support
documentation are available on www.onsemi.com.
Maximum Input Clock Frequency up to 1.5 GHz
Maximum Input Data Rate up to 2.5 Gb/s (Figure 5)
470 ps Maximum Propagation Delay\
1 ps Maximum RMS Jitter
140 ps Maximum Rise/Fall Times
Single Power Supply; VCC = 3.3 V $10%
Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
Internal 50 W Termination Resistor per Input Pin
GND + 50 mV to VCC − 50 mV VCMR Range
Pb−Free Packages are Available
Device DDJ = 10 ps
http://onsemi.com
1
QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB4N
527S
ALYW G
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
VTD0
D0
D0
VTD0
50 W*
50 W*
Q0
Q0
VTD1
D1
D1
VTD1
50 W*
50 W*
Q1
Q1
Figure 1. Functional Block Diagram
*RTIN
TIME (58 ps/div)
Figure 2. Typical Output Waveform at 2.488 Gb/s with
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 3
1
Publication Order Number:
NB4N527S/D









No Preview Available !

NB4N527S Даташит, Описание, Даташиты
NB4N527S
VTD0 D0 D0 VTD0
16 15 14 13
Exposed Pad (EP)
VTD1 1
D1 2
D1 3
VTD1 4
NB4N527S
12 Q0
11 Q0
10 Q1
9 Q1
5 678
GND NC NC VCC
Figure 3. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin Name
I/O
Description
1 VTD1
− Internal 50 W termination pin for D1. (RTIN)
2
D1
LVPECL, CML, LVDS,
Noninverted differential clock/data D1 input (Note 1).
LVCMOS, LVTTL, HSTL
3
D1
LVPECL, CML, LVDS,
Inverted differential clock/data D1 input (Note 1).
LVCMOS, LVTTL, HSTL
4 VTD1
5 GND
− Internal 50 W termination pin for D1. (RTIN)
− 0 V. Ground.
6, 7 NC
No connect.
8 VCC
9 Q1
LVDS Output
Positive Supply Voltage.
Inverted D1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
10 Q1
LVDS Output
Noninverted D1 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
11 Q0
LVDS Output
Inverted D0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
12 Q0
LVDS Output
Noninverted D0 output. Typically loaded with 100 W receiver termination
resistor across differential pair.
13 VTD0
− Internal 50 W termination pin for D0.
14
D0
LVPECL, CML, LVDS,
Noninverted differential clock/data D0 input (Note 1).
LVCMOS, LVTTL, HSTL
15
D0
LVPECL, CML, LVDS,
Inverted differential clock/data D0 input (Note 1).
LVCMOS, LVTTL, HSTL
16 VTD0
− Internal 50 W termination pin for D0.
EP Exposed pad. EP on the package bottom is thermally connected to the die
improved heat transfer out of package. The pad is not electrically connected
to the die, but is recommended to be soldered to GND on the PCB.
1. In the differential configuration when the input termination pins(VTD0/VTD0, VTD1/ VTD1) are connected to a common termination voltage
or left open, and if no signal is applied on D0/D0, D1/D1 input, then the device will be susceptible to self−oscillation.
http://onsemi.com
2









No Preview Available !

NB4N527S Даташит, Описание, Даташиты
NB4N527S
Table 2. ATTRIBUTES
Characteristics
Moisture Sensitivity (Note 2)
Flammability Rating
Oxygen Index: 28 to 34
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Value
Level 1
UL 94 V−0 @ 0.125 in
> 2 kV
> 200 V
> 1 kV
281
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC Positive Power Supply
VI Positive Input
IIN Input Current Through RT (50 W Resistor)
GND = 0 V
GND = 0 V
Static
Surge
VI = VCC
3.8 V
3.8 V
35 mA
70 mA
IOSC
Output Short Circuit Current
Line−to−Line (Q to Q)
Line−to−End (Q or Q to GND)
Q or Q to GND
Q to Q
Continuous
Continuous
12 mA
24
TA Operating Temperature Range
QFN−16
Tstg Storage Temperature Range
qJA Thermal Resistance (Junction−to−Ambient) (Note 3) 0 lfpm
500 lfpm
QFN−16
QFN−16
−40 to +85
−65 to +150
41.6
35.2
°C
°C
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case)
1S2P (Note 3)
Tsol Wave Solder
Pb
Pb−Free
QFN−16
4.0 °C/W
265 °C
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
http://onsemi.com
3










Скачать PDF:

[ NB4N527S.PDF Даташит ]

Номер в каталогеОписаниеПроизводители
NB4N527SDual AnyLevel to LVDS Receiver/Driver/Buffer/TranslatorON Semiconductor
ON Semiconductor

Номер в каталоге Описание Производители
TL431

100 мА, регулируемый прецизионный шунтирующий регулятор

Unisonic Technologies
Unisonic Technologies
IRF840

8 А, 500 В, N-канальный МОП-транзистор

Vishay
Vishay
LM317

Линейный стабилизатор напряжения, 1,5 А

STMicroelectronics
STMicroelectronics

DataSheet26.com    |    2020    |

  Контакты    |    Поиск