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PDF NB4N855S Data sheet ( Hoja de datos )
| Número de pieza | NB4N855S | |
| Descripción | Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator | |
| Fabricantes | ON Semiconductor | |
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NB4N855S
3.3 V, 1.5 Gb/s Dual
AnyLevel™ to LVDS
Receiver/Driver/Buffer/
Translator
Description
NB4N855S is a clock or data Receiver/Driver/Buffer/Translator
capable of translating AnyLevelTM input signal (LVPECL, CML,
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the
distance, noise immunity of the system design, and transmission line
media, this device will receive, drive or translate data or clock signals
up to 1.5 Gb/s or 1.0 GHz, respectively. This device is pin−for−pin
plug in compatible to the SY55855V in a 3.3 V applications.
The NB4N855S has a wide input common mode range of
GND + 50 mV to VCC − 50 mV. This feature is ideal for translating
differential or single−ended data or clock signals to 350 mV typical
LVDS output levels.
The device is offered in a small 10 lead MSOP package. NB4N855S
is targeted for data, wireless and telecom applications as well as high
speed logic interface where jitter and package size are main
requirements.
Application notes, models, and support documentation are available
at www.onsemi.com.
Features
• Guaranteed Input Clock Frequency up to 1.0 GHz
• Guaranteed Input Data Rate up to 1.5 Gb/s
• 490 ps Maximum Propagation Delay
• 1.0 ps Maximum RMS Jitter
• 180 ps Maximum Rise/Fall Times
• Single Power Supply; VCC = 3.3 V ±10%
• Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs
• GND + 50 mV to VCC − 50 mV VCMR Range
http://onsemi.com
1
Micro 10
M SUFFIX
CASE 846B
MARKING
DIAGRAM*
10
855S
AYW
1
A = Assembly Location
Y = Year
W = Work Week
*For additional marking information, refer to
Application Note AND8002/D.
D0 Q0
D0 Q0
D1 Q1
D1 Q1
Functional Block Diagram
Device DDJ = 7 ps
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
TIME (133 ps/div)
Figure 1. Typical Output Waveform at 1.5 Gb/s with K28.5
(VINPP = 100 mV, Input Signal DDJ = 24 ps)
© Semiconductor Components Industries, LLC, 2005
June, 2005 − Rev. 0
1
Publication Order Number:
NB4N855S/D
1 page  
NB4N855S
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, GND = 0 V; (Note 9)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
VOUTPP Output Voltage Amplitude (@ VINPPMIN)fin ≤ 1.0 GHz 230 350
(Figure 3)
fin= 1.5 GHz 200 300
230 350
200 300
230 350
200 300
mV
fDATA Maximum Operating Data Rate
1.5 2.5
1.5 2.5
1.5 2.5
Gb/s
tPLH,
tPHL
Differential Input to Differential Output
Propagation Delay
330 410 490 330 410 490 330 410 490 ps
tSKEW
Duty Cycle Skew (Note 10)
Within −Device Skew (Note 11)
Device to Device Skew (Note 12)
8 45
10 35
20 100
8 45
10 35
20 100
8 45 ps
10 35
20 100
tJITTER
RMS Random Clock Jitter (Note 13) fin = 1.0 GHz
fin = 1.5 GHz
Deterministic Jitter (Note 14) fDATA = 622 Mb/s
fDATA = 1.5 Gb/s
fDATA = 2.488 Gb/s
Crosstalk Induced Jitter (Note 15)
0.5 1
0.5 1
6 15
7 20
10 25
20 40
0.5 1
0.5 1
6 15
7 20
10 25
20 40
0.5 1
0.5 1
6 15
7 20
10 25
20 40
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 16)
100 VCC− 100 VCC− 100 VCC− mV
GND
GND
GND
tr Output Rise/Fall Times @ 250 MHz
tf (20% − 80%)
Q, Q 50 110 180 50 110 180 50 110 180 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. Measured by forcing VINPPMIN with 50% duty cycle clock source and VCC − 1400 mV offset. All loading with an external RL = 100 W across
“D” and “D” of the receiver. Input edge rates 150 ps (20%−80%).
10. See Figure 7 differential measurement of tskew = |tPLH − tPHL| for a nominal 50% differential clock input waveform @ 250 MHz.
11. The worst case condition between Q0/Q0 and Q1/Q1 from either D0/D0 or D1/D1, when both outputs have the same transition.
12. Skew is measured between outputs under identical transition @ 250 MHz.
13. RMS jitter with 50% Duty Cycle clock signal.
14. Deterministic jitter with input NRZ data at PRBS 223−1 and K28.5.
15. Crosstalk Induced Jitter is the additive Deterministic jitter to channel one with channel two active both running at 622 Gb/s PRBS 223 −1 as
an asynchronous signals.
16. Input voltage swing is a single−ended measurement operating in differential mode.
400
350
300
−40°C
250
200 85°C
25°C
150
100
50
0
0 0.5 1 1.5 2 2.5 3
INPUT CLOCK FREQUENCY (GHz)
Figure 3. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) and Temperature (@ VCC = 3.3 V)
http://onsemi.com
5
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