NB6L14M PDF даташит
Спецификация NB6L14M изготовлена «ON Semiconductor» и имеет функцию, называемую «Differential 1:4 CML Fanout Buffer». |
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Детали детали
Номер произв | NB6L14M |
Описание | Differential 1:4 CML Fanout Buffer |
Производители | ON Semiconductor |
логотип |
11 Pages
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NB6L14M
2.5 V/3.3 V 3.0 GHz
Differential 1:4 CML Fanout
Buffer
Multi−Level Inputs with Internal Termination
Description
The NB6L14M is a 3.0 GHz differential 1:4 CML fanout buffer.
The differential inputs incorporate internal 50 W termination resistors
that are accessed through the VT pin. This feature allows the
NB6L14M to accept various logic standards, such as CML, LVCMOS,
LVTTL, CML, or LVDS logic levels. The 16 mA differential CML
outputs provide matching internal 50 W terminations and produce
400 mV output swings when externally terminated with a 50 W
resistor to VCC. The VREFAC reference output can be used to rebias
capacitor−coupled differential or single−ended input signals. The 1:4
fanout design was optimized for low output skew applications.
The NB6L14M is a member of the ECLinPS MAX™ family of high
performance clock and data products.
Features
• Maximum Input Clock Frequency > 3.0 GHz, Typical
• < 20 ps Within Device Output Skew
• 350 ps Typical Propagation Delay
• 90 ps Typical Rise and Fall Times
• Differential CML Outputs, 400 mV Amplitude, Typical
• CML Mode Operating Range: VCC = 2.375 V to 3.63 V with
GND = 0 V
• Internal Input and Output Termination Resistors, 50 W
• VREFAC Reference Output Voltage
• −40°C to +85°C Ambient Operating Temperature
• Available in 3 mm x 3 mm 16 Pin QFN
• These are Pb−Free Devices
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QFN−16
MN SUFFIX
CASE 485G
MARKING
DIAGRAM*
16
1
NB6L
14M
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
DQ
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 0
1
Publication Order Number:
NB6L14M/D
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NB6L14M
Q0 Q0 VCC GND
16 15 14 13
Exposed Pad (EP)
Q0
/Q0
Q1 1
Q1 2
Q2 3
Q2 4
12 IN
11 VT
10 VREFAC
9 IN
IN
VT
/IN
50 W
50 W
EN
DQ
Q1
/Q1
Q2
/Q2
5 678
Q3 Q3 VCC EN
Figure 2. QFN−16 Pinout
(Top View)
VREFAC
CLK Q3
/Q3
Figure 3. Logic Diagram
Table 1. EN TRUTH TABLE
IN
IN
EN
Q0:Q3
Q0:Q3
01
10
xx
+ = On next negative transition of the input signal (IN).
x = Don’t care.
1
1
0
01
10
0+ 1+
Table 2. PIN DESCRIPTION
Pin Name
I/O
Description
1
Q1
CML Output
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
2
Q1
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC .
3
Q2
CML Output
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
4
Q2
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
5
Q3
CML Output
Non−inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
6
Q3
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
7 VCC
− Positive Supply Voltage
8 EN LVTTL/LVCMOS Synchronous Output Enable. When LOW, Q outputs will go LOW and Q outputs will
go HIGH on the next negative transition of IN input. The internal DFF register is
clocked on the falling edge of IN input (see Figure 16). The EN pin has an internal
pullup resistor and defaults HIGH when left open.
9 IN CML, CML, LVDS, Inverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT.
HSTL
10 VREFAC
Output Voltage Reference for capacitor−coupled inputs, only.
11 VT
Internal 100 W center−tapped Termination Pin for IN and IN.
12 IN CML, CML, LVDS, Non−inverted Differential Clock Input. Internal 50 W Resistor to Termination Pin, VT.
HSTL
13 GND
− Negative Supply Voltage
14 VCC
− Positive Supply Voltage
15
Q0
CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
16
Q0
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
− EP
− The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heat−sinking conduit. The pad is not electrically connected to the die, but is
recommended to be electrically and thermally connected to GND on the PC board.
1. In the differential configuration when the input termination pin VT, is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN inputs, then the device will be susceptible to self−oscillation.
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NB6L14M
Table 3. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Mode
Moisture Sensitivity (Note 2)
QFN−16
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Value
> 2 kV
> 200 V
Level 1
UL 94 V−0 @ 0.125 in
Table 4. MAXIMUM RATINGS
Symbol
VCC
VIo
IIN
Parameter
Condition 1
Positive Power Supply
GND = 0 V
Positive Input/Output
GND = 0 V
Input Current
Source or Sink Current (IN/IN)
Condition 2
−0.5 V v VIo v VCC + 0.5 V
Rating
4.0
4.5
"50
Unit
V
V
mA
IVREFAC
IOUT
Sink/Source Current
Output Current
Continuous
Surge
"2.0
25
50
mA
mA
mA
TA Operating Temperature Range
Tstg Storage Temperature Range
qJA
Thermal Resistance
(Junction−to−Ambient) (Note 3)
0 lfpm
500 lfpm
QFN−16
QFN−16
−40 to +85
−65 to +150
42
35
°C
°C
°C/W
°C/W
qJC Thermal Resistance (Junction−to−Case) 2S2P (Note 3) QFN−16
4 °C/W
Tsol Wave Solder
Pb−Free
265 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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