NCP1381 PDF даташит
Спецификация NCP1381 изготовлена «ON Semiconductor» и имеет функцию, называемую «Low Standby High Performance PWM Controller». |
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Детали детали
Номер произв | NCP1381 |
Описание | Low Standby High Performance PWM Controller |
Производители | ON Semiconductor |
логотип |
26 Pages
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NCP1381
Low−Standby High
Performance PWM
Controller
Housed in a SO−14 package, the NCP1381 includes everything
needed to build rugged and efficient Quasi−Resonant (QR) Switching
Power Supplies. When powered by a front−end Power Factor
Correction circuitry, the NCP1381 automatically disconnects the PFC
controller in low output loading conditions (with an adjustable level),
thus improving the standby power. This is particularly well suited for
medium to high power offline applications, e.g. notebook adapters.
When the current setpoint falls below a given value, e.g. the output
power demand diminishes, the IC automatically enters the so−called
skip cycle mode and provides excellent efficiency at light loads.
Because this occurs at an adjustable low peak current together with a
proprietary Soft−Skipt technique, no acoustic noise takes place. Skip
cycle also offers the ability to easily select the maximum switching
frequency at which foldback and standby take place.
The NCP1381 also features several efficient protection options like
a) a short−circuit / overload detection independent of the auxiliary
voltage b) an auto−recovery brown−out detection and c) an input to
externally latch the circuit in case of Overvoltage Protection or Over
Temperature Protection.
Features
• Current−Mode Quasi−Resonant Operation
• Adjustable Line Over Power Protection
• Extremely Low Startup Current of 15 mA Maximum
• Soft−Skip Cycle Capability at Adjustable Peak Currents
• Plateau Sensing Overvoltage
• Brown−Out Protection
• Maximum tON Limitation
• Overpower Protection by current Sense Offset
• Internal 5 ms Soft−Start Management
• Short−Circuit Protection Independent from Auxiliary Level
• External Latch Input Pin for an OTP Signal
• Go−To−Standby Signal for the PFC Front Stage
• True Frequency (tON + tOFF) Clamp Circuit
• Low and Noiseless, No−Load Standby Power
• Internal Leading Edge Blanking
• +500 mA / −800 mA Peak Current Drive Capability
• 5 V / 10 mA Reference Voltage
• This is a Pb−Free Device
Typical Applications
• High Power AC/DC Adapters for Notebooks, etc
• Offline Battery Chargers
• Set−Top Boxes Power Supplies, TV, Monitors, etc
http://onsemi.com
HIGH PERFORMANCE QR
CONTROLLER FEATURING PFC
SHUTDOWN
14
1
MARKING
DIAGRAM
14
SOIC−14
D SUFFIX
CASE 751A
1
NCP1381G
AWLYWW
NCP1381G = Specific Device Code
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
ADJ_GTS
BO
DMG
Timer
Skip/OVP
FB
CS
1
2
3
4
5
6
7
14 nc
13 nc
12 Ref
11 GTS
10 VCC
9 DRV
8 GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 25 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 3
1
Publication Order Number:
NCP1381/D
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NCP1381
TYPICAL APPLICATION EXAMPLE
HV
PFC Stage
+
To PFC’s VCC
+
OVP
BO
DMG
NCP1381
GTS_ADJ 1
2
14
13
3 12
4 11
5 10
69
Skip
7
8
Vref
+
+
Vout
GTS_ADJ
OPP
Figure 1. Typical Application Example
PIN FUNCTION DESCRIPTION
Pin# Symbol
1 GTS_ADJ
GTS Level Adjustment
2 BO
Brown−out
3
DMG
Detects the Zero Voltage
Crossing Point
4 Timer
Fault Timer
5 Skip/OVP
Adjust the Skip Level
6 FB
Feedback Signal
7 CS
Current Sense Pin
8 GND
9 DRV
The IC Ground
The Driver Output
10 VCC
VCC Input
11 GTS Directly Powers the PFC
Frontend Stage
12 Reference
13 NC
14 NC
Reference Voltage
−
−
Description
An internal comparator senses the signal applied to this pin (typically a portion of
FB signal) to detect the standby condition for GTS.
By connecting this pin to a resistive divider, the controller ensures operation at a
safe mains level.
This pin detects the core reset event but also permanently senses the Flyback
plateau, offering a clean OVP detection.
Connecting a capacitor to this pin adjusts the fault timer.
This pin alters the default skip cycle level and offers a mean to latchoff the con-
troller when externally brought above 4 V.
An optocoupler collector pulls this pin down to regulate. When the current set-
point falls below an adjustable level, the controller skips cycles.
This pin cumulates two different functions: the standard sense function plus an
adjustable offset voltage providing the adequate level of Overpower Protection.
−
With a drive capability of $500 mA/800 mA, the NCP1381 can drive large Qg
MOSFETs.
The controller accepts voltages up to 20 V and features an UVLO of 10 V typical.
This pin directly powers the PFC controller by routing the PWM VCC to the PFC
VCC. In standby (defined by GTS_ADJ), fault and BO conditions, this pin is open
and the PFC is no longer supplied.
This pin offers a 5 V reference voltage sourcing up to 10 mA.
Not Connected
Not Connected
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2
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NCP1381
INTERNAL CIRCUIT ARCHITECTURE
5 mA
VDD
ADJ_GTS 1
ADJ_GTS Section
+
250 mV
−
+
RST
Timer
BO 2
S
CLK Q
Q
R
+
−
+ BOComp. VDD
240 mV/
500 mV
8 ms No DMG
Timeout
+
+
−
VCC Management
UVLO, Latchoff
Timer IP
Flag
BO
DMG 3
VlatchDem
+−
+
4 ms
Delayed
1 Shot
to
Latch
−
+
DRV
3 ms
1 Shot
S
CLK Q
Q
DRV
Timer 4
VDD
DRV
VDD
/4
+ Vth
DRV
+ 1shSohtot
−
+
tON > 45 ms?
Fault
SS
R
Prioritary
Reset
VDD
tON + tOFF=8 ms
Max Fsw
Clamping
+
−
+
Skip
UVLO
+
Vref
BO
GTS
Conf. ?
Timer
IPFlag
Fault /
Startup
Skip/ 5
OVP
FB 6
CS 7
LEB
OPP
Offset
I/V 85 mS
VDD
30 mA
−
+
Skip
Section
25 k
+
Latchoff
+
−
Vlatch
Soft−Start Ended
+
−
Timer
+
−
VTimSS
+
SSCap
+
VTimFault
VDD
S
Q
Q
R
IP Flag
GTS
Switches are Kept Closed until NOR
Output Goes Low
VDD
4 V Reset
Plateau
Sensing
Soft−Skip
Soft−Start
SSCap
Figure 2. Internal Circuit Architecture
http://onsemi.com
3
12 Ref
11 GTS
10 VCC
9 Drv
8 GND
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