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NCP3418A PDF даташит

Спецификация NCP3418A изготовлена ​​​​«ON Semiconductor» и имеет функцию, называемую «Dual Bootstrapped 12 V MOSFET Driver».

Детали детали

Номер произв NCP3418A
Описание Dual Bootstrapped 12 V MOSFET Driver
Производители ON Semiconductor
логотип ON Semiconductor логотип 

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NCP3418A Даташит, Описание, Даташиты
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NCP3418, NCP3418A
Dual Bootstrapped 12 V
MOSFET Driver with
Output Disable
The NCP3418 and NCP3418A are dual MOSFET gate drivers
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. Each of the drivers is
capable of driving a 3000 pF load with a 25 ns propagation delay and a
20 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal,
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 30 V, with transient voltages as high as 35 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
The NCP3418A is identical to the NCP3418 except that there is no
internal charge pump diode.
The NCP3418 is pin−to−pin compatible with Analog Devices
ADP3418 with the following advantages:
Faster Rise and Fall Times
Internal Charge Pump Diode Reduces Cost and Parts Count
Thermal Shutdown for System Protection
Integrated OVP
Internal Pulldown Resistor Suppresses Transient Turn On of Either
MOSFET
Features
Anti Cross−Conduction Protection Circuitry
Floating Top Driver Accommodates Boost Voltages of up to 30 V
One Input Signal Controls Both the Upper and Lower Gate Outputs
Output Disable Control Turns Off Both MOSFETs
Complies with VRM 10.x Specifications
Undervoltage Lockout
Thermal Shutdown
Thermally Enhanced Package Available
http://onsemi.com
MARKING
DIAGRAMS
8
1
SO−8
D SUFFIX
CASE 751
8
3418
ALYW
8
3418A
ALYW
11
88
SO−8 EP
3418
3418A
8
PD SUFFIX
ALYW
ALYW
1 CASE 751AC
1
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
PIN CONNECTIONS
1
BST
IN
OD
VCC
8
DRVH
SW
PGND
DRVL
ORDERING INFORMATION
Device
Package
Shipping
NCP3418D
NCP3418DR2
SO−8
SO−8
98 Units/Rail
2500 Tape & Reel
NCP3418ADR2 SO−8 2500 Tape & Reel
NCP3418ADR2G SO−8 2500 Tape & Reel
NCP3418PD SO−8 EP 98 Units/Rail
NCP3418PDR2 SO−8 EP 2500 Tape & Reel
NCP3418APDR2 SO−8 EP 2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2004
May, 2004 − Rev. 10
1
Publication Order Number:
NCP3418/D









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NCP3418A Даташит, Описание, Даташиты
NCP3418, NCP3418A
VCC
4
Not present in
the NCP3418A
1 BST
IN 2
4V +
OD 3
Nonoverlap
+
1.5 V
8 DRVH
100 k
7 SW
5 DRVL
120 k
6 PGND
Figure 1. NCP3418/A Block Diagram
PIN DESCRIPTION
Pin Symbol
Description
1 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this
bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value is between
100 nF and 1.0 mF. An external diode will be needed with the NCP3418A.
2 IN Logic−Level Input. This pin has primary control of the drive outputs.
3 OD Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
4 VCC Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.
5
DRVL
Output drive for the lower MOSFET.
6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7 SW Switch Node. Connect to the source of the upper MOSFET.
8 DRVH Output drive for the upper MOSFET.
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NCP3418A Даташит, Описание, Даташиты
NCP3418, NCP3418A
MAXIMUM RATINGS*
Rating
Operating Ambient Temperature, TA
Operating Junction Temperature, TJ (Note 1)
Package Thermal Resistance: SO−8
Junction−to−Case, RqJC
Junction−to−Ambient, RqJA (2−Layer Board)
Package Thermal Resistance: SO−8 EP
Junction−to−Ambient, RqJA (Note 2)
Storage Temperature Range, TS
Lead Temperature Soldering (10 sec): Reflow (SMD styles only)
Standard (Note 3)
Lead Free (Note 4)
JEDEC Moisture Sensitivity Level
SO−8 (240 peak profile)
SO−8 (260 peak profile)
SO−8 EP (240 peak profile)
SO−8 EP (260 peak profile)
1. Internally limited by thermal shutdown, 150°C min.
2. Rating applies when soldered to an appropriate thermal area on the PCB.
3. 60 − 180 seconds minimum above 183°C.
4. 60 − 180 seconds minimum above 237°C.
*The maximum package power dissipation must be observed.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
Value
0 to 85
0 to 150
45
123
50
−65 to 150
240 peak
260 peak
1
1
1
3
Unit
°C
°C
°C/W
°C/W
°C/W
°C
°C
MAXIMUM RATINGS
Pin Symbol
VCC
BST
Pin Name
Main Supply Voltage Input
Bootstrap Supply Voltage Input
SW
DRVH
Switching Node
(Bootstrap Supply Return)
High−Side Driver Output
DRVL
Low−Side Driver Output
IN DRVH and DRVL Control Input
OD Output Disable
PGND
Ground
NOTE: All voltages are with respect to PGND except where noted.
VMAX
15 V
30 V wrt/PGND
35 V v 50 ns wrt/PGND
15 V wrt/SW
30 V
BST + 0.3 V
35 V v 50 ns wrt/PGND
15 V wrt/SW
VCC + 0.3 V
VCC + 0.3 V
VCC + 0.3 V
0V
VMIN
−0.3 V
−0.3 V wrt/SW
−1.0 V DC
−10 V< 200 ns
−0.3 V wrt/SW
−0.3 V DC
−2.0 V < 200 ns
−0.3 V
−0.3 V
0V
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