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PDF NCP5211A Data sheet ( Hoja de datos )
| Número de pieza | NCP5211A | |
| Descripción | Low Voltage Synchronous Buck Controller | |
| Fabricantes | ON Semiconductor | |
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NCP5211A
Low Voltage Synchronous
Buck Controller
The NCP5211A is a low voltage synchronous buck controller. It
contains all required circuitry for a synchronous buck converter using
external N−Channel MOSFETs. High current internal gate drivers are
capable of driving low RDS(on) NFETs for better efficiency. The
NCP5211A is in a 14 pin package to minimize PCB area.
The NCP5211A provides overcurrent protection, undervoltage
lockout, soft start and built in adaptive nonoverlap. The NCP5211A is
adjustable over a frequency range of 150 kHz to 750 kHz. This gives
the designer more flexibility to make efficiency and component size
compromises. The NCP5211A will operate on a single supply or a
separate boost supply.
Features
• Switching Regulator Controller
− N−Channel Synchronous Buck Design
− 1.0 Amp Gate Drive Capability
− 200 ns Transient Response
− Programmable Operating Frequency of 150 kHz−750 kHz
− 0.8 V 1% Internal Reference
− Lossless Inductor Sensing Overcurrent Protection
− Cycle−by−Cycle Short Circuit Protection
− Programmable Soft Start
− 40 ns GATE Rise and Fall Times (3.3 nF Load)
− 70 ns Adaptive FET Nonoverlap Time
− Differential Remote Sense Capability
• System Power Management
− Operation with a Conversion Rail of 5.0 V or 12 V
− Undervoltage Lockout
− On/Off Control Through Use of the COMP Pin
− Max Duty Cycle Clamped to 70% for Forward Converter Control
Applications
• Set Top Devices
• Forward Converters
• Buck Converters
• Point of Load Regulation
http://onsemi.com
SOIC−14
D SUFFIX
CASE 751A
MARKING
DIAGRAM
14
NCP5211A
BWLYWW
1
B = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
PIN CONNECTIONS
1
GATE(H)
BST
LGND
VFFB
VFB
COMP
SGND
PGND
GATE(L)
VC
IS+
IS−
VCC
ROSC
ORDERING INFORMATION
Device
Package
Shipping†
NCP5211AD
SO−14
55 Units/Rail
NCP5211ADR2 SO−14 2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2003
December, 2003 − Rev. 3
1
Publication Order Number:
NCP5211A/D
1 page  
NCP5211A
PACKAGE PIN DESCRIPTION
PIN NO.
PIN SYMBOL
1 GATE(H)
2 BST
3 LGND
4 VFFB
5 VFB
6 COMP
7 SGND
8 ROSC
9 VCC
10 IS−
11 IS+
12 VC
13 GATE(L)
14 PGND
FUNCTION
High Side Switch FET driver pin. Capable of delivering peak currents of 1.0 A.
Power supply input for the high side driver.
Reference ground. All control circuits are referenced to this pin. IC substrate connection.
Input for the PWM comparator.
Error amplifier input.
Error Amp output. PWM Comparator reference input. A capacitor to LGND provides error amp
compensation.
Internal reference is connected to this ground. Connect directly at the load for ground remote
sensing.
A resistor from this pin to SGND sets switching frequency.
Input Power Supply Pin. It supplies power to control circuitry. A 0.1 µF decoupling cap is
recommended.
Negative input for overcurrent comparator.
Positive input for overcurrent comparator.
Power supply input for the low side driver.
Low Side Synchronous FET driver pin. Capable of delivering peak currents of 1.0 A.
High Current ground for the GATE(H) and GATE(L) pins.
VFFB
COMP
VFB
SGND
VCC
IS+
IS−
LGND
0.5 V
PWM Comparator
Σ
Ramp
PWM FF
Reset Dominant
RQ
Error Amp
−
+
0.8 V
STOP
START
S
Q
OSC
START
ROSC
UVLO
Comparator
VSTART
OC FF
Reset Dominant
RQ
OC
Comparator
60 mV
0.4 V
+ COMP Comp
−
SQ
Figure 2. NCP5211A Block Diagram
BST
GATE(H)
VC
GATE(L)
PGND
ROSC
http://onsemi.com
5
5 Page 
NCP5211A
Once the dissipation is known, the heat sink thermal
impedance can be calculated to prevent the specified
maximum case or junction temperatures from being exceeded
at the highest ambient temperature. Power dissipation has two
primary contributors: conduction losses and switching losses.
The control or upper MOSFET will display both switching
and conduction losses. The synchronous or lower MOSFET
will exhibit only conduction losses because it switches into
nearly zero voltage. However, the body diode in the
synchronous MOSFET will suffer diode losses during the
non−overlap time of the gate drivers.
For the upper or control MOSFET, the power dissipation
can be approximated from:
PD,CONTROL + (IRMS,CNTL2 @ RDS(on))
) (ILo,MAX @ QswitchńIg @ VIN @ fSW)
) (Qossń2 @ VIN @ fSW) ) (VIN @ QRR @ fSW)
The first term represents the conduction or IR losses when
the MOSFET is ON while the second term represents the
switching losses. The third term is the losses associated with
the control and synchronous MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
Where IRMS,CNTL is the RMS value of the trapezoidal
current in the control MOSFET:
IRMS,CNTL + ǸD @ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN
) ILo,MIN2)ń3]1ń2
ILo,MAX is the maximum output inductor current:
ILo,MAX + IO,MAXń2 ) DILoń2
ILo,MIN is the minimum output inductor current:
ILo,MIN + IO,MAXń2 * DILoń2
IO,MAX is the maximum converter output current.
D is the duty cycle of the converter:
D + VOUTńVIN
∆ILo is the peak−to−peak ripple current in the output
inductor of value Lo:
DILo + (VIN * VOUT) @ Dń(Lo @ fSW)
RDS(on) is the ON resistance of the MOSFET at the
applied gate drive voltage.
Qswitch is the post gate threshold portion of the
gate−to−source charge plus the gate−to−drain charge. This
may be specified in the data sheet or approximated from the
gate−charge curve as shown in the Figure 13.
Qswitch + Qgs2 ) Qgd
ID
VGATE
VGS_TH
QGS1 QGS2
QGD
VDRAIN
Figure 13. MOSFET Switching Characteristics
Ig is the output current from the gate driver IC.
VIN is the input voltage to the converter.
fsw is the switching frequency of the converter.
QG is the MOSFET total gate charge to obtain RDS(on)
(commonly specified in the data sheet).
Vg is the gate drive voltage.
QRR is the reverse recovery charge of the lower MOSFET.
Qoss is the MOSFET output charge specified in the data
sheet.
For the lower or synchronous MOSFET, the power
dissipation can be approximated from:
PD,SYNCH + (IRMS,SYNCH2 @ RDS(on))
) (Vfdiode @ IO,MAXń2 @ t_nonoverlap @ fSW)
The first term represents the conduction or IR losses when
the MOSFET is ON and the second term represents the diode
losses that occur during the gate non−overlap time.
All terms were defined in the previous discussion for the
control MOSFET with the exception of:
IRMS,SYNCH + Ǹ1 * D
@ [(ILo,MAX2 ) ILo,MAX @ ILo,MIN ) ILo,MIN2)ń3]1ń2
where:
Vfdiode is the forward voltage of the MOSFET’s intrinsic
diode at the converter output current.
t_nonoverlap is the non−overlap time between the upper
and lower gate drivers to prevent cross conduction. This
time is usually specified in the data sheet for the control
IC.
When the MOSFET power dissipations are known, the
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature
qT t (TJ * TA)ńPD
where;
θT is the total thermal impedance (θJC + θSA).
http://onsemi.com
11
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| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet NCP5211A.PDF ] | |
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