NCP5214 PDF даташит
Спецификация NCP5214 изготовлена «ON Semiconductor» и имеет функцию, называемую «Notebook DDR Power Controller». |
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Детали детали
Номер произв | NCP5214 |
Описание | Notebook DDR Power Controller |
Производители | ON Semiconductor |
логотип |
14 Pages
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NCP5214
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2−in−1 Notebook DDR
Power Controller
The NCP5214 2−in−1 Notebook DDR Power Controller is
specifically designed as a total power solution for notebook DDR
memory system. This IC combines the efficiency of a PWM
controller for the VDDQ supply with the simplicity of linear
regulators for the VTT termination voltage and the buffered low
noise reference. This IC contains a synchronous PWM buck
controller for driving two external NFETs to form the DDR memory
supply voltage (VDDQ). The DDR memory termination regulator
output voltage (VTT) and the buffered VREF are internally set to
track at the half of VDDQ. An internal power good voltage monitor
tracks VDDQ output and notifies the user whether the VDDQ output
is within target range. Protective features include soft−start
circuitries, undervoltage monitoring of supply voltage, VDDQ
overcurrent protection, VDDQ overvoltage and undervoltage
protections, and thermal shutdown. The IC is packaged in DFN−22.
Features
• Incorporates VDDQ, VTT Regulator, Buffered VREF
• Adjustable VDDQ Output
• VTT and VREF Track VDDQ/2
• Operates from Single 5.0 V Supply
• Supports VDDQ Conversion Rails from 5.0 V to 24 V
• Power−saving Mode for High Efficiency at Light Load
• Integrated Power FETs with VTT Regulator Sourcing/Sinking 1.5 A
DC and 2.4 A Peak Current
• Buffered Low Noise 15 mA VREF Output
• All External Power MOSFETs are N−channel
• <5.0 mA Current Consumption During Shutdown
• Fixed Switching Frequency of 400 kHz
• Soft−start Protection for VDDQ and VTT
• Undervoltage Monitor of Supply Voltage
• Overvoltage Protection and Undervoltage Protection for VDDQ
• Short−circuit Protection for VDDQ and VTT
• Thermal Shutdown
• Housed in DFN−22
Typical Applications
• Notebook DDR/DDR2 Memory Supply and Termination Voltage
• Active Termination Busses (SSTL−18, SSTL−2, SSTL−3)
http://onsemi.com
MARKING
DIAGRAM
1
22 DFN−22
MN SUFFIX
NCP5214
CASE 506AF
AWLYYWW
1
NCP5214 = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
PIN CONNECTIONS
VDDQEN
VTTEN
FPWM
SS
VTTGND
VTT
VTTI
FBVTT
AGND
DDQREF
VCCA
PGND
BGDDQ
VCCP
SWDDQ
TGDDQ
BOOST
OCDDQ
PGOOD
VTTREF
FBDDQ
COMP
(Top View)
NOTE: Pin 23 is the thermal pad on
the bottom of the device.
ORDERING INFORMATION
Device
Package
Shipping†
NCP5214MNR2 DFN−22 2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2005
April, 2005 − Rev. P0
1
Publication Order Number:
NCP5214/D
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VDDQEN
VTTEN
FPWM
VDDQEN
VTTEN
FPWM
SS
CSS
5VCC
PWRGD
VTT
0.9 V, 2.4 Apk
COUT2
Ceramic
22 mF x2
5VCC
PGOOD
VTT
FBVTT
VTTGND
VCCA
0.9 V, 15 mA
VREF
VTTREF
DDQREF
NCP5214
CL1
RL1
OCDDQ
BOOST
5VCC
NCP5214
VCCP
TGDDQ
SWDDQ
BGDDQ
PGND1
M1
L
1.8 mH
M2
VIN
5 V to 24 V
(Battery/
Adapter)
VDDQ
1.8 V, 10 A
COUT1
POSCAP
150 mF x2
COMP
CZ1
CP1
RZ1
FBDDQ
CZ2
R1
RZ2
R2
AGND
VTTI
Figure 1. Typical Application Diagram
http://onsemi.com
2
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NCP5214
5VCC
VDDQEN
VTTEN
FPWM
VCCA
VCCA
VOLTAGE &
CURRENT
REFERENCE
VREF
VREFGD
VDDQEN
VTTEN
FPWM
VCCAGD
VOCDDQGD
FAULT
TSD
CONTROL
LOGIC
THERMAL
SHUTDOWN
VCCP
VBOOST
VCCP
BOOST
VREF
+
−
VOCDDQ
VREF
+
−
VCCA
SS
5VCC
VDDQEN
VTTEN
INREGDDQ
ILIM
+
−
VOFFSET
VDDQ
PWM
LOGIC
Power−
Saving
Loop
Control
FBDDQ
SWDDQ
NEGATIVE CURRENT
DETECTION
+
−
VREF
IREF
VBOOST
RL1
OCDDQ
TGDDQ
VCCP
SWDDQ
BGDDQ
PGND
PGND
VFBDDQ
VIN
CBULK
5VCC
M3
VDDQ
L
COUT1
M4
PGOOD
PGND
VOCDDQ
VTTI
VTTREF
VTTREF
COUT3
+
−
GND
OSC
Adaptive
Ramp
PWM−
COMP
+−
+
−
UVLO VFBDDQ
OVLO +
−
VREF
VREF
+
A−
Current
Limit &
Soft−Start
+
−
SC2PWR VDDQEN
Deadband
Control
VTTEN
INREGDDQ
VTT
Regulation
Control
SC2GND
+
−
VCCA
M1
VTTGND
VCCA
M2
VTTGND
VTTGND
COMP
CZ1
RZ1
CP1
FBDDQ
CZ2
RZ2
DDQREF
R1
R2
VTTI
VTT
VTT
COUT2
PGND
VTTGND
FBVTT
AGND
VTTGND
Figure 2. Detailed Block Diagram
http://onsemi.com
3
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