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PDF HM51S4170D Data sheet ( Hoja de datos )
| Número de pieza | HM51S4170D | |
| Descripción | (HM514170D / HM514270D) Dynamic RAM | |
| Fabricantes | Hitachi Semiconductor | |
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HM514170D, HM514270D Series
HM51S4170D, HM51S4270D Series
262,144-word × 16-bit Dynamic RAM
ADE-203-672 (Z)
Preliminary
Rev. 0.0
Oct. 18, 1996
Description
The Hitachi HM51(S)4170D, HM51(S)4270D Series are CMOS dynamic RAM organized as 262,144-word ×
16-bit. HM51(S)4170D, HM51(S)4270D Series have realized higher density, higher performance and various
functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies.
The HM51(S)4170D, HM51(S)4270D Series offer fast page mode as a high speed access mode. They have
the package variations of standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII.
Internal refresh timer enables HM51S4170D, HM51S4270D Series self refresh operation.
Features
• Single 5 V supply: 5 V ± 10%
• Access time: 60 ns/70 ns/80 ns (max)
• Low power dissipation
Active mode: 825 mW/660 mW/578 mW (max) (HM51(S)4170D Series)
825 mW/770 mW/688 mW (max) (HM51(S)4270D Series)
Standby mode: 11 mW (max)
1.1 mW (max) (L-version)
• Fast page mode capability
• Refresh cycles
1024 refresh cycles: 16 ms (HM51(S)4170D Series)
128 ms (L-version) (HM51(S)4170DL Series)
512 refresh cycles: 8 ms (HM51(S)4270D Series)
128 ms (L-version) (HM51(S)4270DL Series)
• 2 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
Preliminary: This document contains information on a new product. Specifications and information
contained herein are subject to change without notice.
1 page  
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Pin Arrangement
HM51(S)4170D Series, HM51(S)4270D Series
HM514270DJ/DLJ Series
HM51S4270DJ/DLJ Series
VCC
I/O0
I/O1
I/O2
I/O3
VCC
I/O4
I/O5
I/O6
I/O7
NC
LWE
UWE
RAS
NC
A0
A1
A2
A3
VCC
1 40
2 39
3 38
4 37
5 36
6 35
7 34
8 33
9 32
10 31
11 30
12 29
13 28
14 27
15 26
16 25
17 24
18 23
19 22
20 21
(Top view)
VSS
I/O15
I/O14
I/O13
I/O12
VSS
I/O11
I/O10
I/O9
I/O8
NC
NC
CAS
OE
A8
A7
A6
A5
A4
VSS
Pin Description
Pin name Function
A0 to A8
Address input
— Refresh address A0 to A8
— Row address A0 to A8
— Column address A0 to A8
I/O0 to I/O15 Data input/output
RAS
Row address strobe
CAS
Column address strobe
UWE / LWE Read/write enable
OE Output enable
VCC Power supply
VSS Ground
NC No connection
HM514270DTT/DLTT Series
HM51S4270DTT/DLTT Series
VCC 1
I/O0 2
I/O1 3
I/O2 4
I/O3 5
VCC 6
I/O4 7
I/O5 8
I/O6 9
I/O7 10
44 VSS
43 I/O15
42 I/O14
41 I/O13
40 I/O12
39 VSS
38 I/O11
37 I/O10
36 I/O9
35 I/O8
NC
LWE
UWE
RAS
NC
A0
A1
A2
A3
VCC
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
(Top view)
NC
NC
CAS
OE
A8
A7
A6
A5
A4
VSS
5
5 Page 
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HM51(S)4170D Series, HM51(S)4270D Series
Capacitance (Ta = 25°C, VCC = 5 V ± 10%)
Parameter
Symbol Typ Max Unit Notes
Input capacitance (Address)
CI1 — 5 pF 1
Input capacitance (Clocks)
CI2 — 7 pF 1
Output capacitance (Data-in, Data-out)
CI/O — 10 pF 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)*1, *14, *15, *17, *18
Test Conditions
• Input rise and fall time: 5 ns
• Input timing reference levels: 0.8 V, 2.4 V
• Input levels: 0 V, 3 V
• Output load: 2 TTL gate + CL (100 pF) (Including scope and jig)
11
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| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HM51S4170D.PDF ] | |
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