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PDF NGD15N41CLT4 Data sheet ( Hoja de datos )
| Número de pieza | NGD15N41CLT4 | |
| Descripción | Ignition IGBT | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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NGD15N41CLT4,
NGB15N41CLT4,
NGP15N41CL
Preferred Device
Ignition IGBT
15 Amps, 410 Volts
N−Channel DPAK, D2PAK and TO−220
This Logic Level Insulated Gate Bipolar Transistor (IGBT) features
monolithic circuitry integrating ESD and Over−Voltage clamped
protection for use in inductive coil drivers applications. Primary uses
include Ignition, Direct Fuel Injection, or wherever high voltage and
high current switching is required.
• Ideal for Coil−on−Plug Applications
• DPAK Package Offers Smaller Footprint and Increased Board Space
• Gate−Emitter ESD Protection
• Temperature Compensated Gate−Collector Voltage Clamp Limits
Stress Applied to Load
• Integrated ESD Diode Protection
• New Design Increases Unclamped Inductive Switching (UIS) Energy
Per Area
• Low Threshold Voltage to Interface Power Loads to Logic or
Microprocessor Devices
• Low Saturation Voltage
• High Pulsed Current Capability
• Optional Gate Resistor (RG) and Gate−Emitter Resistor (RGE)
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Collector−Emitter Voltage
Collector−Gate Voltage
Gate−Emitter Voltage
Collector Current−Continuous
@ TC = 25°C − Pulsed
ESD (Human Body Model)
R = 1500 Ω, C = 100 pF
VCES
VCER
VGE
IC
ESD
440 VDC
440 VDC
15 VDC
15 ADC
50 AAC
kV
8.0
ESD (Machine Model) R = 0 Ω, C = 200 pF
ESD 800 V
Total Power Dissipation @ TC = 25°C
Derate above 25°C
PD 107 Watts
0.71 W/°C
Operating and Storage Temperature Range
TJ, Tstg −55 to
+175
°C
http://onsemi.com
15 AMPS
410 VOLTS
VCE(on) 3 2.1 V @
IC = 10 A, VGE . 4.5 V
C
G RG
RGE
4
12
3
E
DPAK
CASE 369C
STYLE 2
12
3
4 D2PAK
CASE 418B
STYLE 4
4
TO−220AB
CASE 221A
STYLE 9
1
2
3
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 8 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2004
March, 2004 − Rev. 5
1
Publication Order Number:
NGD15N41CL/D
1 page  
NGD15N41CLT4, NGB15N41CLT4, NGP15N41CL
3
2.5 IC = 15 A
2 IC = 10 A
1.5 IC = 5 A
1
0.5
TJ = 150°C
10000
1000
100
10
1
Ciss
Coss
Crss
0
3 4 5 6 7 8 9 10
GATE TO EMITTER VOLTAGE (VOLTS)
Figure 7. Collector−to−Emitter Voltage versus
Gate−to−Emitter Voltage
0
0 20 40 60 80 100 120 140 160 180 200
VCE, COLLECTOR TO EMITTER VOLTAGE (VOLTS)
Figure 8. Capacitance Variation
2
1.8
Mean + 4 σ
Mean
1.6
1.4
1.2 Mean − 4 σ
1
0.8
0.6
0.4
0.2
0
−50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
Figure 9. Gate Threshold Voltage versus
Temperature
30
25
20 L = 2 mH
VCC = 50 V
VGE = 5 V
RG = 1000 Ω
15
L = 3 mH
10
L = 6 mH
5
0
−50 −25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
Figure 11. Typical Open Secondary Latch
Current versus Temperature
30
VCC = 50 V
25 VGE = 5 V
RG = 1000 Ω
20
L = 2 mH
L = 3 mH
15
10
L = 6 mH
5
0
−50 −25 0 25 50 75 100 125 150 175
TEMPERATURE (°C)
Figure 10. Minimum Open Secondary Latch
Current versus Temperature
12
VCC = 300 V
10 VGE = 5 V
RG = 1000 Ω
8
IC = 10 A
L = 300 µH
6
4
tf
td(off)
2
0
−50 −30 −10 10 30 50 70 90 110 130 150
TEMPERATURE (°C)
Figure 12. Inductive Switching Fall Time
versus Temperature
http://onsemi.com
5
5 Page 
NGD15N41CLT4, NGB15N41CLT4, NGP15N41CL
PACKAGE DIMENSIONS
D2PAK
CASE 418B−04
ISSUE H
C
E
−B−
V
W
4
123
S
A
−T−
SEATING
PLANE
G
K
W
J
D 3 PL
0.13 (0.005) M T B M
H
VARIABLE
CONFIGURATION
ZONE
L
M
R
M
N
L
U
M
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 418B−01 THRU 418B−03 OBSOLETE,
NEW STANDARD 418B−04.
INCHES
DIM MIN MAX
A 0.340 0.380
B 0.380 0.405
C 0.160 0.190
D 0.020 0.035
E 0.045 0.055
F 0.310 0.350
G 0.100 BSC
H 0.080 0.110
J 0.018 0.025
K 0.090 0.110
L 0.052 0.072
M 0.280 0.320
N 0.197 REF
P 0.079 REF
R 0.039 REF
S 0.575 0.625
V 0.045 0.055
MILLIMETERS
MIN MAX
8.64 9.65
9.65 10.29
4.06 4.83
0.51 0.89
1.14 1.40
7.87 8.89
2.54 BSC
2.03 2.79
0.46 0.64
2.29 2.79
1.32 1.83
7.11 8.13
5.00 REF
2.00 REF
0.99 REF
14.60 15.88
1.14 1.40
STYLE 4:
PIN 1. GATE
2. COLLECTOR
P 3. EMITTER
4. COLLECTOR
L
F
VIEW W−W
1
F
VIEW W−W
2
F
VIEW W−W
3
SOLDERING FOOTPRINT*
8.38
0.33
10.66
0.42
1.016
0.04
6.096
0.24
17.02
0.67
3.05
0.12
ǒ ǓSCALE 3:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet NGD15N41CLT4.PDF ] | |
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